SystemVerilog jobs
SystemVerilog: the modern language for designing and checking computer chips. Astera Labs, SpaceX, Tenstorrent, K2 Space and Anduril Industries have the most open roles mentioning SystemVerilog right now.
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191 open roles · 14 posted in the last 7 days · 4% remote · 37 companies hiring · $202K median advertised salary · checked Nov 15 against employer career pages
Job titles in SystemVerilog roles
Bars show the share of these 191 roles; one role can count in several rows.
Newest SystemVerilog jobs
- Principal Design Verifiction EngineerSambaNova · 🇺🇸San Jose, California, United States$180K - $225KLead and abovePythonC++Machine Learning
- Senior FPGA Verification EngineerAnduril Industries · 🇺🇸Waltham, Massachusetts, United States · +2 more locations$191K - $254KSeniorPythonC++Linux
- Senior Firmware EngineerAnduril Industries · 🇺🇸Waltham, Massachusetts, United States$191K - $254KSeniorPythonLinuxMATLAB
- Senior Embedded EngineerAnduril Industries · 🇺🇸Waltham, Massachusetts, United States$191K - $254KSeniorPythonLinuxMATLAB
- FPGA Engineering Intern (Summer 2027)Reliable Robotics · 🇺🇸Mountain View, CA$128KInternPythonC++Verilog
- FPGA EngineerAnysignal · 🇺🇸Los Angeles, CA$130K - $170KPythonC++Bash
- Senior FPGA Prototyping EngineerK2 Space · 🇺🇸United States - Remote · +1 more location$120K - $225KRemoteSeniorPythonVerilogTest planning
- Senior ASIC Design Verification EngineerK2 Space · 🇺🇸United States - Remote · +1 more location$170K - $250KRemoteSeniorPythonC++CI/CD
- Principal ASIC Design Verification EngineerK2 Space · 🇺🇸United States - Remote · +1 more location$190K - $285KRemoteLead and abovePythonC++CI/CD
- Senior Hardware Design EngineerArago · 🇫🇷Paris Offices—HybridSeniorMachine LearningVerilogFrench
- Staff Engineer, Digital ASIC Design — Storage ControllersSK hynix memory solutions America Inc. · 🇺🇸San Jose—Lead and aboveMachine LearningVerilogStorage systems
- RTL Design Engineer, Networking / NoCOpenAI · 🇺🇸San Francisco$287K - $485KHybridVerilogHigh-performance computingASIC
- Principal Design Verification Engineer (AI Fabric Switches)Astera Labs · 🇺🇸San Jose, California, United States$185K - $240KLead and abovePythonC++AI
- Sr/Staff Digital Design EngineerLightmatter · 🇨🇦Toronto, ON · +2 more locations$123K - $175KLead and abovePythonBashVerilog
- Validation and Verification Engineer, Aviation EngineeringSkyryse · 🇺🇸El Segundo, CA$120K - $145KPythonC++MATLAB
- DFT EngineerTenstorrent · 🇺🇸Austin, Texas, United States; Fort Collins, Colorado, Uni…—VerilogHardware interfacesCompilers
- FPGA EngineerTomorrow.io · 🇺🇸Golden, Colorado, United States—VerilogGenerative AITest planning
- Principal Formal Verification EngineerAstera Labs · 🇮🇳Bengaluru, Karnataka, India—Lead and abovePythonVerilogPerl
- Silicon Design LeadOpenAI · 🇺🇸San Francisco$287K - $485KHybridLead and aboveVerilogThreat modelingFirmware
- Mixed-signal IC Design EngineerArago · 🇫🇷Paris Offices—Machine LearningVerilogFrench
- Principal PCS/PMA RTL Design EngineerAstera Labs · 🇺🇸San Jose, California, United States$185K - $240KLead and abovePythonVerilogPerl
- FPGA Design Engineer (R5347)Shield AI · 🇺🇸Seattle, WA, US$187K - $280KCI/CDVerilogGit
- Software Engineer, Embedded Applications (R5068)Shield AI · 🇺🇸Dallas, TX, US$198K - $296KC++VerilogSecurity clearance
- Technical Lead Digital Design EngineerAstera Labs · 🇺🇸San Jose, California, United States$160K - $200KLead and abovePythonVerilogTest planning
- Staff / Principal ASIC Design EngineerAstera Labs · 🇮🇱Haifa District, Israel · +1 more location—Lead and abovePythonVerilogPerl
- Senior ASIC Design EngineerAstera Labs · 🇮🇱Haifa District, Israel · +1 more location—SeniorPythonVerilogPerl
- Hardware Engineers: RTL Implementation and Evaluation WorkflowsTerac · 🇺🇸United States—RemoteVerilogHardware testingASIC
- FPGA EngineerAnduril Industries · 🇺🇸Broomfield, Colorado, United States; Fort Collins, Colora…$144K - $192KPythonC++Docker
- Senior Design Verification Engineer, AI HardwareTenstorrent · 🇷🇸Belgrade, Serbia—SeniorAIVerilogFirmware
- Design Verification Engineer, New GradSambaNova · 🇺🇸San Jose, California, United States$120K - $150KJuniorPythonVerilogPerl
- Junior Emulation EngineerCelero Communications, Inc. · 🇦🇷Cordoba, Argentina—JuniorPythonLinuxVerilog
- Principal Design Verification Engineer- SerDes/PHY IPAstera Labs · 🇺🇸San Jose, California, United States$207K - $230KLead and abovePythonVerilogPerl
- Synthesis & STA Engineer – High-Speed SerDesAstera Labs · 🇺🇸San Jose, California, United States$160K - $200KPythonVerilogPerl
- Senior Design Verification EngineerAstera Labs · 🇺🇸San Jose, California, United States · +3 more locations$148K - $165KSeniorPythonVerilogPerl
- Principal Verification EngineerAstera Labs · 🇺🇸San Jose, California, United States · +1 more location$185K - $230KLead and abovePythonC++Verilog
- Staff Engineer, RTL Design, AI HardwareTenstorrent · 🇷🇸Belgrade, Serbia—Lead and aboveAIVerilogCompilers
- Senior Engineer, RTL Design, AI HardwareTenstorrent · 🇷🇸Belgrade, Serbia—SeniorAIVerilogCompilers
- Director, Silicon Logical DesignGraphcore · 🇮🇳Bengaluru, India · +1 more location—Lead and aboveVerilogPerformance managementHardware interfaces
- Sr. FPGA Design EngineerReliable Robotics · 🇺🇸Mountain View, CA$215K - $300KSeniorAgileVerilogFirmware
- Principal Physical Design EngineerAstera Labs · 🇮🇳Bengaluru, Karnataka, India · +1 more location—Lead and abovePythonVerilogPerl
- Senior Digital ASIC Design Engineer - DSP/Analog/SerDesCelero Communications, Inc. · 🇨🇦Ottawa, Ontario, Canada · +2 more locations—SeniorPythonMATLABVerilog
- Staff ML Accelerator ArchitectWaymo · 🇺🇸Mountain View, CA, USA; New York, New York, USA$251K - $310KLead and aboveMachine LearningVerilogCompilers
- FPGA Engineer (Starshield)SpaceX · 🇺🇸Hawthorne, CA$125K - $160KPythonC++Bash
- SoC EngineerOpenAI · 🇺🇸San Francisco$287K - $485KHybridVerilogFirmwareHardware interfaces
- Tech Lead Analog Mixed-Signal IC Layout EngineerAstera Labs · 🇸🇬Singapore, Singapore—Lead and abovePythonC++Verilog
- Senior Analog Mixed-Signal IC Layout EngineerAstera Labs · 🇸🇬Singapore, Singapore—SeniorPythonC++Verilog
- Sr. ASIC Design Engineer (Silicon Engineering)SpaceX · 🇺🇸Palo Alto, CA · +3 more locations$175K - $280KSeniorPythonVerilogFirmware
- ASIC Design Engineer (Silicon Engineering)SpaceX · 🇺🇸Palo Alto, CA$135K - $175KPythonC++Bash
- Digital ASIC Design EngineerAttoTude · 🇩🇪Nuremberg, Germany—PythonMATLABVerilog
- FPGA Engineer, EWAnduril Industries · 🇺🇸Costa Mesa, California, United States$146K - $194KPythonLinuxCI/CD
- Formal Verification EngineerTenstorrent · 🇺🇸🇪🇸Santa Clara, California, United States; Spain—PythonC++Verilog
- Sr. RF Silicon Software Engineer (RFIC Engineering)SpaceX · 🇺🇸Redmond, WA$165K - $270KSeniorPythonC++Verilog
- FPGA/ASIC Design Engineer (Silicon Engineering)SpaceX · 🇺🇸Irvine, CA · +1 more location$125K - $160KPythonC++Bash
- RF Silicon Software Engineer (RFIC Engineering)SpaceX · 🇺🇸Redmond, WA$125K - $165KPythonC++Verilog
- Silicon Emulation EngineerWaymo · 🇹🇼Taipei, Taiwan; Hsinchu, Taiwan · +1 more location—PythonC++Linux
- Design Verification Emulation, HardwareRiver AI Inc. · 🇺🇸Austin, TX, Palo Alto, CA$200K - $420KPythonC++CI/CD
- Tech Lead Engineer, Design VerificationAstera Labs · 🇺🇸San Jose, California, United States$176K - $195KLead and abovePythonVerilogPowerShell
- Senior RTL Design EngineerEnvision Employment Solutions · New Cairo City, Cairo Governorate, Egypt—SeniorPythonVerilogPerl
- VLSI Functional Safety Hardware ArchitectEnvision Employment Solutions · New Cairo City, Cairo Governorate, Egypt—VerilogPCB designASIC
- FPGA Associate (Winter 2027)Astranis · 🇺🇸San Francisco—VerilogFPGARTL design
- FPGA Associate (Summer 2027)Astranis · 🇺🇸San Francisco—VerilogFPGARTL design
- FPGA Intern (Summer 2027)Astranis · 🇺🇸San Francisco—InternVerilogFPGARTL design
- FPGA Intern (Winter 2027)Astranis · 🇺🇸San Francisco—InternVerilogFPGARTL design
- Design Verification Tech Lead- SerDes/PHY IPAstera Labs · 🇺🇸San Jose, California, United States$160K - $200KLead and abovePythonVerilogPerl
- DFT EngineerAstera Labs · 🇮🇳Bengaluru, Karnataka, India$133K - $185KVerilogHardware interfacesASIC
- Principal Logic Design Engineer - UALink IP/SubsystemAstera Labs · 🇮🇳Bengaluru, Karnataka, India—Lead and aboveVerilogFirmwareHardware interfaces
- Lead Logic Design EngineerAstera Labs · 🇮🇳Bengaluru, Karnataka, India—Lead and aboveVerilogHardware interfacesASIC
- Principal DFT EngineerCelero Communications, Inc. · 🇺🇸Irvine, California, United States$200K - $240KLead and abovePythonLinuxVerilog
- Midcore Design Verification EngineerTenstorrent · 🇺🇸🇪🇸Santa Clara, California, United States; Spain—PythonC++Verilog
- Front End Design Verification EngineerTenstorrent · 🇺🇸🇪🇸Santa Clara, California, United States; Spain—PythonC++Verilog
- Principal RTL Design Engineer, IO & Memory SystemsSambaNova · 🇺🇸Austin, Texas, United States; San Jose, California, Unite…$180K - $255KLead and aboveMachine LearningVerilogFirmware
- Manager Design VerificationAstera Labs · 🇮🇱Tel Aviv-Yafo, Tel Aviv District, Israel—VerilogFirmwareHardware interfaces
- Research Engineer, AI for Chip DesignOpenAI · 🇺🇸San Francisco$380K - $500KHybridAIVerilogLLM evaluation
- Senior Digital Design EngineerAstera Labs · 🇨🇦Toronto, Ontario, CanadaCA$140K - CA$155KSeniorPythonVerilogPerl
- Principal Emulation EngineerAstera Labs · 🇺🇸San Jose, California, United States · +1 more location$207K - $230KLead and abovePythonVerilogPerl
- Software Engineer, AI for Chip DesignOpenAI · 🇺🇸San Francisco$266K - $468KHybridPythonAIVerilog
- 2027 – Internship or Graduate, FPGA EngineeringQube Research & Technologies · 🇺🇸London, Paris, New York · +1 more location—InternPythonC++Verilog
- FPGA EngineerEpirus · 🇺🇸Torrance, California, United States$124K - $144KPythonAgileMATLAB
- Sr. Staff Engineer, CPU (Front-End) VerificationTenstorrent · 🇺🇸Austin, Texas, United States; Santa Clara, California, Un…—Lead and aboveC++VerilogCompilers
- Senior Digital Design Engineer, Air Dominance and StrikeAnduril Industries · 🇺🇸Costa Mesa, California, United States$166K - $220KSeniorPythonLinuxCI/CD
- Senior FPGA Verification Engineer, Air Dominance and StrikeAnduril Industries · 🇺🇸Costa Mesa, California, United States$166K - $220KSeniorPythonLinuxCI/CD
- Mixed-signal Verification EngineerArago · 🇫🇷Paris Offices—PythonVerilogmacOS
- Staff Silicon Verification EngineerGraphcore · 🇮🇳Bengaluru, India—Lead and abovePythonJavaScriptC++
- Senior Silicon Verification EngineerGraphcore · 🇮🇳Bengaluru, India—SeniorPythonJavaScriptC++
- Senior Silicon Logical Design Engineer - Multiple VacanciesGraphcore · 🇮🇳Bengaluru, India—SeniorPythonVerilogData centers
- Formal Verification and RTL Design Software EngineerAstera Labs · 🇺🇸San Jose, California, United States$160K - $200KPythonLLMCI/CD
- Tech Lead– Verification Methodology/CADAstera Labs · 🇮🇳Bengaluru, Karnataka, India—Lead and abovePythonC++Linux
- Senior FPGA Verification EngineerIonQ · 🇬🇧Oxford, England, United Kingdom—SeniorPythonVerilogFinancial modeling
- Senior RTL Design EngineerSambaNova · 🇺🇸Austin, Texas, United States; San Jose, California, Unite…$120K - $200KSeniorPythonLinuxVerilog
- Principal RTL Design EngineerSambaNova · 🇺🇸Austin, Texas, United States; San Jose, California, Unite…$180K - $255KLead and abovePythonVerilogHardware interfaces
- FPGA Verification Engineer, Air Dominance and StrikeAnduril Industries · 🇺🇸Costa Mesa, California, United States$146K - $194KPythonLinuxCI/CD
- Digital Design Engineer, Air Dominance and StrikeAnduril Industries · 🇺🇸Costa Mesa, California, United States$146K - $194KPythonLinuxCI/CD
- Director of ASIC Design VerificationSambaNova · 🇺🇸San Jose, California, United States$270K - $340KLead and abovePythonMachine LearningVerilog
- Design Verification EngineerSambaNova · 🇺🇸San Jose, California, United States$120K - $200KPythonMachine LearningVerilog
- Senior Hardware Design EngineerSambaNova · 🇺🇸Austin, Texas, United States; San Jose, California, Unite…$120K - $200KSeniorPythonLinuxVerilog
- FPGA RF Signal Processing EngineerMuon Space · 🇺🇸San Jose, CA$190K - $212KRustPythonC++
- Senior FPGA Engineer, Networking & SecurityMuon Space · 🇺🇸San Jose, CA$213K - $237KSeniorVerilogSecurity clearanceNetwork engineering
- (Senior) FPGA EngineerDistance · 🇫🇮Helsinki (HQ), Finland—HybridSeniorPythonVerilogEnglish
- Staff Design Verification EngineerCerebras · 🇺🇸Sunnyvale, CA$225K - $270KLead and abovePython.NETVerilog
- Senior FPGA Engineer (TS/SCI)K2 Space · 🇺🇸Los Angeles, CA$120K - $225KSeniorRustPythonC++
Showing the newest 100. See all 191 in search
Who is hiring for SystemVerilog roles
Where SystemVerilog roles are
- 🇺🇸United States130
- 🇺🇸California94
- 🇺🇸San Francisco Bay Area69
- 🌏Asia-Pacific23
- 🇪🇺Europe21
- 🇮🇳India18
- 🇺🇸Texas16
- 🇮🇳Bangalore16
- 🇺🇸Austin, TX15
- 🇺🇸Los Angeles, CA14
A role that lists several places is counted in each of them.
What SystemVerilog roles pay, by level
| Level in the title | Median advertised salary | Roles counted |
|---|---|---|
| No level in the title | $180K | 39 |
| Senior | $193K | 34 |
| Lead and above | $220K | 32 |
Medians of the midpoints of advertised yearly US-dollar ranges; a level needs at least 15 such roles. Advertised, not verified pay.
Jobs you can get with SystemVerilog
| Kind of work | Open jobs asking for SystemVerilog | Median advertised pay |
|---|---|---|
| Hardware engineer | 148 | $198K |
| Design verification engineer | 70 | $210K |
| ASIC and chip design engineer | 63 | $218K |
| Test and validation engineer | 50 | $208K |
| FPGA engineer | 37 | $172K |
| Analog and mixed-signal engineer | 12 | $200K |
| Software engineer | 10 | $218K |
| Tech lead and team lead | 5 | – |
Skills asked together with SystemVerilog
Verilog (100%), RTL design (78%), Python (77%), ASIC (66%), Hardware interfaces (50%), UVM (45%), Firmware (43%), FPGA (35%) of the 191 open postings that name SystemVerilog.
Companies hiring for SystemVerilog
SystemVerilog salariesQuestions about SystemVerilog jobs
- What is SystemVerilog?
- The modern language for designing and checking computer chips. 191 open roles on Jobs Every Hour ask for it as of Nov 15, 2026.
- How many SystemVerilog jobs are open right now?
- There are 191 open SystemVerilog jobs at 37 companies on Jobs Every Hour as of Nov 15, 2026. 14 of them were posted in the last seven days. The list is rebuilt every hour from the employers' own careers pages.
- Which companies have the most SystemVerilog jobs?
- Right now the most openings are at Astera Labs (39), SpaceX (19), Tenstorrent (16), K2 Space (14) and Anduril Industries (12). The ranking changes as companies open and close roles.
- Are there remote SystemVerilog jobs?
- 8 of the 191 open SystemVerilog jobs (4%) are listed as remote. Remote roles are often limited to certain countries or time zones, so check the location line of each job.
- What do SystemVerilog jobs pay?
- The median advertised salary is $202K, based on 106 open roles that publish a yearly US-dollar range. The middle half of those roles advertise between $170K and $228K. These are advertised ranges, not verified pay. Most employers here are technology companies, so the figures run above the wider market for the same work.
- Is it hard to get an SystemVerilog job?
- 8 of the 191 open SystemVerilog jobs (4%) are for beginners: junior roles and internships. Of the 137 postings that state experience, the median asks for 5 years. 37 companies are hiring and 14 roles were posted in the last seven days. Matching your resume to the skills each posting names helps most; the free resume builder shows the match.
- How is AI changing SystemVerilog jobs?
- 41 of the 191 open SystemVerilog jobs (21%) ask for AI or machine-learning skills, most often Machine Learning, Computer Vision, AI. Employers still list 191 such roles today at 37 companies. Counted from the postings' own text on Nov 15, 2026.
- What skills do SystemVerilog jobs ask for?
- Most often Verilog (100%), SystemVerilog (100%), RTL design (78%), Python (77%), ASIC (66%) of the 191 open postings, counted from their own text on Nov 15, 2026.
- Which job titles come up most in SystemVerilog jobs?
- Design Verification Engineer (10), FPGA Engineer (7), Senior FPGA Engineer (7), Senior FPGA Verification Engineer (5), Senior Design Verification Engineer (5): the most common titles among the 191 open roles, without the level and place notes in brackets.
- Are SystemVerilog jobs in demand in 2026?
- 191 SystemVerilog jobs are open on Jobs Every Hour today at 37 companies, 0.1% of all 148,162 open jobs here; 14 were posted in the last seven days. The median advertised salary is $202K. 8 (4%) can be done remotely.
- How do I apply for SystemVerilog jobs?
- Open a job and press “Apply on company site”. You go straight to the employer's own careers page and apply there. Jobs Every Hour needs no account and charges nothing for applying.
Narrow down SystemVerilog jobs
By place
- SystemVerilog jobs in the United States 130
- SystemVerilog jobs in California 94
- 🌏SystemVerilog jobs in Asia-Pacific 23
- SystemVerilog jobs in Europe 21
- SystemVerilog jobs in India 18
- SystemVerilog jobs in Texas 16
- SystemVerilog jobs in Bangalore 16
- SystemVerilog jobs in Austin, TX 15
- SystemVerilog jobs in Los Angeles, CA 14
- SystemVerilog jobs in Seattle, WA 12
- SystemVerilog jobs in Israel 10
- SystemVerilog jobs in Canada 8
- SystemVerilog jobs in San Francisco Bay Area















