Design Verification Engineer, New Grad

As a new grad Design Verification Engineer, you'll write testbenches, tests, checkers, and coverage in SystemVerilog and UVM for RDU features. You'll run regressions, debug simulation failures, and work with RTL designers to find and fix bugs before tape-out. Responsibilities Write and execute verification plans for chip-level control and initialization features Build SystemVerilog and UVM testbench components…

SambaNova has 75 open roles right now, 4 of them remote. Most are in Engineering, Marketing & Community and Operations. The median advertised salary across its roles with a published range is $218K. See all its roles