🇺🇸SystemVerilog jobs in California
94 open roles mentioning SystemVerilog in California as of Nov 15, 2026. Astera Labs, SpaceX, SambaNova, OpenAI and Tenstorrent have the most. The median advertised salary is $202K.
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Skills asked for in SystemVerilog roles in California
Job titles in SystemVerilog roles in California
Bars show the share of these 94 roles; one role can count in several rows.
- Principal Design Verifiction EngineerSambaNova · 🇺🇸San Jose, California, United States$180K - $225KLead and abovePythonC++Machine Learning
- Senior FPGA Verification EngineerAnduril Industries · 🇺🇸Goleta, California, United States$191K - $254KSeniorPythonC++Linux
- FPGA Engineering Intern (Summer 2027)Reliable Robotics · 🇺🇸Mountain View, CA$128KInternPythonC++Verilog
- FPGA EngineerAnysignal · 🇺🇸Los Angeles, CA$130K - $170KPythonC++Bash
- Staff Engineer, Digital ASIC Design — Storage ControllersSK hynix memory solutions America Inc. · 🇺🇸San Jose—Lead and aboveMachine LearningVerilogStorage systems
- RTL Design Engineer, Networking / NoCOpenAI · 🇺🇸San Francisco$287K - $485KHybridVerilogHigh-performance computingASIC
- Principal Design Verification Engineer (AI Fabric Switches)Astera Labs · 🇺🇸San Jose, California, United States$185K - $240KLead and abovePythonC++AI
- Sr/Staff Digital Design EngineerLightmatter · 🇺🇸Mountain View, CA$164K - $222KLead and abovePythonBashVerilog
- Validation and Verification Engineer, Aviation EngineeringSkyryse · 🇺🇸El Segundo, CA$120K - $145KPythonC++MATLAB
- DFT EngineerTenstorrent · 🇺🇸Austin, Texas, United States; Fort Collins, Colorado, Uni…—VerilogHardware interfacesCompilers
- Silicon Design LeadOpenAI · 🇺🇸San Francisco$287K - $485KHybridLead and aboveVerilogThreat modelingFirmware
- Principal PCS/PMA RTL Design EngineerAstera Labs · 🇺🇸San Jose, California, United States$185K - $240KLead and abovePythonVerilogPerl
- Technical Lead Digital Design EngineerAstera Labs · 🇺🇸San Jose, California, United States$160K - $200KLead and abovePythonVerilogTest planning
- Design Verification Engineer, New GradSambaNova · 🇺🇸San Jose, California, United States$120K - $150KJuniorPythonVerilogPerl
- Principal Design Verification Engineer- SerDes/PHY IPAstera Labs · 🇺🇸San Jose, California, United States$207K - $230KLead and abovePythonVerilogPerl
- Synthesis & STA Engineer – High-Speed SerDesAstera Labs · 🇺🇸San Jose, California, United States$160K - $200KPythonVerilogPerl
- Senior Design Verification EngineerAstera Labs · 🇺🇸San Jose, California, United States · +1 more location$148K - $165KSeniorPythonVerilogPerl
- Principal Verification EngineerAstera Labs · 🇺🇸San Jose, California, United States · +1 more location$185K - $230KLead and abovePythonC++Verilog
- Sr. FPGA Design EngineerReliable Robotics · 🇺🇸Mountain View, CA$215K - $300KSeniorAgileVerilogFirmware
- Senior Digital ASIC Design Engineer - DSP/Analog/SerDesCelero Communications, Inc. · 🇺🇸Irvine, CA · +1 more location$150K - $250KSeniorPythonMATLABVerilog
- Staff ML Accelerator ArchitectWaymo · 🇺🇸Mountain View, CA, USA; New York, New York, USA$251K - $310KLead and aboveMachine LearningVerilogCompilers
- FPGA Engineer (Starshield)SpaceX · 🇺🇸Hawthorne, CA$125K - $160KPythonC++Bash
- SoC EngineerOpenAI · 🇺🇸San Francisco$287K - $485KHybridVerilogFirmwareHardware interfaces
- Sr. ASIC Design Engineer (Silicon Engineering)SpaceX · 🇺🇸Palo Alto, CA · +1 more location$175K - $280KSeniorPythonVerilogFirmware
- ASIC Design Engineer (Silicon Engineering)SpaceX · 🇺🇸Palo Alto, CA$135K - $175KPythonC++Bash
- FPGA Engineer, EWAnduril Industries · 🇺🇸Costa Mesa, California, United States$146K - $194KPythonLinuxCI/CD
- Formal Verification EngineerTenstorrent · 🇺🇸🇪🇸Santa Clara, California, United States; Spain—PythonC++Verilog
- FPGA/ASIC Design Engineer (Silicon Engineering)SpaceX · 🇺🇸Irvine, CA$125K - $160KPythonC++Bash
- Design Verification Emulation, HardwareRiver AI Inc. · 🇺🇸Austin, TX, Palo Alto, CA$200K - $420KPythonC++CI/CD
- Tech Lead Engineer, Design VerificationAstera Labs · 🇺🇸San Jose, California, United States$176K - $195KLead and abovePythonVerilogPowerShell
- FPGA Associate (Winter 2027)Astranis · 🇺🇸San Francisco—VerilogFPGARTL design
- FPGA Associate (Summer 2027)Astranis · 🇺🇸San Francisco—VerilogFPGARTL design
- FPGA Intern (Summer 2027)Astranis · 🇺🇸San Francisco—InternVerilogFPGARTL design
- FPGA Intern (Winter 2027)Astranis · 🇺🇸San Francisco—InternVerilogFPGARTL design
- Design Verification Tech Lead- SerDes/PHY IPAstera Labs · 🇺🇸San Jose, California, United States$160K - $200KLead and abovePythonVerilogPerl
- Principal DFT EngineerCelero Communications, Inc. · 🇺🇸Irvine, California, United States$200K - $240KLead and abovePythonLinuxVerilog
- Midcore Design Verification EngineerTenstorrent · 🇺🇸🇪🇸Santa Clara, California, United States; Spain—PythonC++Verilog
- Front End Design Verification EngineerTenstorrent · 🇺🇸🇪🇸Santa Clara, California, United States; Spain—PythonC++Verilog
- Principal RTL Design Engineer, IO & Memory SystemsSambaNova · 🇺🇸Austin, Texas, United States; San Jose, California, Unite…$180K - $255KLead and aboveMachine LearningVerilogFirmware
- Research Engineer, AI for Chip DesignOpenAI · 🇺🇸San Francisco$380K - $500KHybridAIVerilogLLM evaluation
- Principal Emulation EngineerAstera Labs · 🇺🇸San Jose, California, United States$207K - $230KLead and abovePythonVerilogPerl
- Software Engineer, AI for Chip DesignOpenAI · 🇺🇸San Francisco$266K - $468KHybridPythonAIVerilog
- FPGA EngineerEpirus · 🇺🇸Torrance, California, United States$124K - $144KPythonAgileMATLAB
- Sr. Staff Engineer, CPU (Front-End) VerificationTenstorrent · 🇺🇸Austin, Texas, United States; Santa Clara, California, Un…—Lead and aboveC++VerilogCompilers
- Senior Digital Design Engineer, Air Dominance and StrikeAnduril Industries · 🇺🇸Costa Mesa, California, United States$166K - $220KSeniorPythonLinuxCI/CD
- Senior FPGA Verification Engineer, Air Dominance and StrikeAnduril Industries · 🇺🇸Costa Mesa, California, United States$166K - $220KSeniorPythonLinuxCI/CD
- Formal Verification and RTL Design Software EngineerAstera Labs · 🇺🇸San Jose, California, United States$160K - $200KPythonLLMCI/CD
- Senior RTL Design EngineerSambaNova · 🇺🇸Austin, Texas, United States; San Jose, California, Unite…$120K - $200KSeniorPythonLinuxVerilog
- Principal RTL Design EngineerSambaNova · 🇺🇸Austin, Texas, United States; San Jose, California, Unite…$180K - $255KLead and abovePythonVerilogHardware interfaces
- FPGA Verification Engineer, Air Dominance and StrikeAnduril Industries · 🇺🇸Costa Mesa, California, United States$146K - $194KPythonLinuxCI/CD
Showing the newest 50. See all 94 in search
Who is hiring for SystemVerilog roles in California
What SystemVerilog roles in California pay, by level
| Level in the title | Median advertised salary | Roles counted |
|---|---|---|
| No level in the title | $180K | 32 |
| Senior | $186K | 20 |
| Lead and above | $219K | 26 |
Medians of the midpoints of advertised yearly US-dollar ranges; a level needs at least 15 such roles. Advertised, not verified pay.
Questions about SystemVerilog jobs in California
- How many SystemVerilog jobs in California are open right now?
- There are 94 open SystemVerilog jobs in California at 23 companies on Jobs Every Hour as of Nov 15, 2026. 6 of them were posted in the last seven days. The list is rebuilt every hour from the employers' own careers pages.
- Which companies have the most SystemVerilog jobs in California?
- Right now the most openings are at Astera Labs (17), SpaceX (10), SambaNova (8), Anduril Industries (6) and OpenAI (6). The ranking changes as companies open and close roles.
- Are there remote SystemVerilog jobs in California?
- None of the 94 open SystemVerilog jobs in California are listed as remote at the moment. Remote roles appear here as soon as employers post them.
- What do SystemVerilog jobs in California pay?
- The median advertised salary is $202K, based on 79 open roles that publish a yearly US-dollar range. The middle half of those roles advertise between $170K and $233K. These are advertised ranges, not verified pay. Most employers here are technology companies, so the figures run above the wider market for the same work.
- Is it hard to get one of the SystemVerilog jobs in California?
- 4 of the 94 open SystemVerilog jobs in California (4%) are for beginners: junior roles and internships. Of the 75 postings that state experience, the median asks for 5 years. 23 companies are hiring and 6 roles were posted in the last seven days. Matching your resume to the skills each posting names helps most; the free resume builder shows the match.
- How is AI changing SystemVerilog jobs in California?
- 22 of the 94 open SystemVerilog jobs in California (23%) ask for AI or machine-learning skills, most often Machine Learning, Computer Vision, AI. Employers still list 94 such roles today at 23 companies. Counted from the postings' own text on Nov 15, 2026.
- What skills do SystemVerilog jobs in California ask for?
- Most often Verilog (100%), SystemVerilog (100%), RTL design (81%), Python (80%), ASIC (67%) of the 94 open postings, counted from their own text on Nov 15, 2026.
- Which job titles come up most in SystemVerilog jobs in California?
- Design Verification Engineer (7), FPGA Engineer (5), Senior FPGA Engineer (5), Principal DFT Engineer (3), Senior FPGA Verification Engineer (2): the most common titles among the 94 open roles, without the level and place notes in brackets.
- Are SystemVerilog jobs in California in demand in 2026?
- 94 SystemVerilog jobs in California are open on Jobs Every Hour today at 23 companies, 0.1% of all 148,162 open jobs here; 6 were posted in the last seven days. The median advertised salary is $202K. 0 (0%) can be done remotely.
- How do I apply for SystemVerilog jobs in California?
- Open a job and press “Apply on company site”. You go straight to the employer's own careers page and apply there. Jobs Every Hour needs no account and charges nothing for applying.
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