RTL design jobs
RTL design: describing a chip’s logic in code before it becomes a physical design. Astera Labs, Tenstorrent, SpaceX, Graphcore and K2 Space have the most open roles mentioning RTL design right now.
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367 open roles · 16 posted in the last 7 days · 4% remote · 42 companies hiring · $212K median advertised salary · checked Nov 15 against employer career pages
Job titles in RTL design roles
Bars show the share of these 367 roles; one role can count in several rows.
Newest RTL design jobs
- Senior FPGA Verification EngineerAnduril Industries · 🇺🇸Waltham, Massachusetts, United States · +2 more locations$191K - $254KSeniorPythonC++Linux
- Senior Firmware EngineerAnduril Industries · 🇺🇸Waltham, Massachusetts, United States$191K - $254KSeniorPythonLinuxMATLAB
- Senior Embedded EngineerAnduril Industries · 🇺🇸Waltham, Massachusetts, United States$191K - $254KSeniorPythonLinuxMATLAB
- Senior FPGA Prototyping EngineerK2 Space · 🇺🇸United States - Remote · +1 more location$120K - $225KRemoteSeniorPythonVerilogTest planning
- Senior ASIC Physical Design EngineerK2 Space · 🇺🇸United States - Remote · +1 more location$170K - $250KRemoteSeniorAnalog designCompilersASIC
- Senior ASIC Design Verification EngineerK2 Space · 🇺🇸United States - Remote · +1 more location$170K - $250KRemoteSeniorPythonC++CI/CD
- Principal ASIC Physical Design EngineerK2 Space · 🇺🇸United States - Remote · +2 more locations$190K - $280KRemoteLead and aboveAnalog designASICRTL design
- Principal ASIC Design Verification EngineerK2 Space · 🇺🇸United States - Remote · +1 more location$190K - $285KRemoteLead and abovePythonC++CI/CD
- Principal ASIC Synthesis and Timing EngineerK2 Space · 🇺🇸United States - Remote$190K - $280KRemoteLead and aboveAnalog designASICRTL design
- Sr. Physical Design Flow & Methodology EngineerLightmatter · 🇺🇸Boston, MA$154K - $175KSeniorPythonLLMCI/CD
- Senior Hardware Design EngineerArago · 🇫🇷Paris Offices—HybridSeniorMachine LearningVerilogFrench
- Staff Engineer, Digital ASIC Design — Storage ControllersSK hynix memory solutions America Inc. · 🇺🇸San Jose—Lead and aboveMachine LearningVerilogStorage systems
- RTL Design Engineer, Networking / NoCOpenAI · 🇺🇸San Francisco$287K - $485KHybridVerilogHigh-performance computingASIC
- Engineer, CPU Performance VerificationTenstorrent · 🇺🇸Austin, Texas, United States; Santa Clara, California, Un…—PythonC++Compilers
- Principal Design Verification Engineer (AI Fabric Switches)Astera Labs · 🇺🇸San Jose, California, United States$185K - $240KLead and abovePythonC++AI
- Sr/Staff Digital Design EngineerLightmatter · 🇨🇦Toronto, ON · +2 more locations$123K - $175KLead and abovePythonBashVerilog
- Physical Design and CAD EngineerAstera Labs · 🇺🇸San Jose, California, United States$160K - $200KPythonHardware interfacesCompilers
- DFT EngineerTenstorrent · 🇺🇸Austin, Texas, United States; Fort Collins, Colorado, Uni… · +1 more location—VerilogHardware interfacesCompilers
- FPGA EngineerTomorrow.io · 🇺🇸Golden, Colorado, United States—VerilogGenerative AITest planning
- Principal Design EngineerAstera Labs · 🇺🇸San Jose, California, United States$185K - $240KLead and abovePythonFirmwareHardware interfaces
- Senior Microarchitecture ResearcherIonQ · 🇺🇸Bothell, Washington, United States; Boulder, Colorado, Un…$188K - $282KSeniorTechnical writingFinancial modelingRTL design
- Principal Formal Verification EngineerAstera Labs · 🇮🇳Bengaluru, Karnataka, India—Lead and abovePythonVerilogPerl
- Manager, Capital MarketsFigure Lending · 🇺🇸Remote; Reno, NV; Charlotte, NC$128K - $192KRemoteSQLTableauExcel
- Silicon Design LeadOpenAI · 🇺🇸San Francisco$287K - $485KHybridLead and aboveVerilogThreat modelingFirmware
- Mixed-signal IC Design EngineerArago · 🇫🇷Paris Offices—Machine LearningVerilogFrench
- Staff Cloud Hypervisor Engineer, ComputeCrusoe · 🇺🇸Sunnyvale, CA - US$215K - $260KLead and aboveRustC++Linux
- Principal PCS/PMA RTL Design EngineerAstera Labs · 🇺🇸San Jose, California, United States$185K - $240KLead and abovePythonVerilogPerl
- EDA Cloud & Developer Infrastructure EngineerOpenAI · 🇺🇸San Francisco$287K - $485KHybridPythonPostgreSQLTerraform
- Technical Lead Digital Design EngineerAstera Labs · 🇺🇸San Jose, California, United States$160K - $200KLead and abovePythonVerilogTest planning
- Sr. Software Engineer, Systems Framework & InfrastructureTenstorrent · 🇨🇦Toronto, Ontario, Canada—SeniorPythonC++Machine Learning
- Principal Physical Design CAD EngineerAstera Labs · 🇮🇱Tel Aviv-Yafo, Tel Aviv District, Israel · +1 more location—Lead and abovePythonLLMCI/CD
- Staff/ Principal Physical Design STA EngineerAstera Labs · 🇮🇱Haifa District, Israel · +1 more location—Lead and abovePythonPerlData centers
- Staff / Principal ASIC Design EngineerAstera Labs · 🇮🇱Haifa District, Israel · +1 more location—Lead and abovePythonVerilogPerl
- DFT EngineerAstera Labs · 🇮🇱Haifa District, Israel · +2 more locations—PythonPerlVideo editing
- Staff DFT EngineerAstera Labs · 🇮🇱Haifa District, Israel · +1 more location—Lead and abovePythonPerlVideo editing
- Principal DFT EngineerAstera Labs · 🇮🇱Haifa District, Israel · +2 more locations—Lead and abovePythonPerlHardware interfaces
- Physical Design Team LeadAstera Labs · 🇮🇱Haifa District, Israel · +1 more location—Lead and abovePythonPerlHardware interfaces
- Senior ASIC Design EngineerAstera Labs · 🇮🇱Haifa District, Israel · +1 more location—SeniorPythonVerilogPerl
- Hardware Engineers: RTL Implementation and Evaluation WorkflowsTerac · 🇺🇸United States—RemoteVerilogHardware testingASIC
- FPGA EngineerAnduril Industries · 🇺🇸Broomfield, Colorado, United States; Fort Collins, Colora…$144K - $192KPythonC++Docker
- Electrical Engineer- SDR HardwareAstranis · 🇺🇸San Francisco$115K - $180KPythonPCB designAnalog design
- DSP Integration Test EngineerAttoTude · 🇺🇸Menlo Park, CA—PythonC++Docker
- SoC Clocking Specialist (Physical Design)EnCharge AI · 🇮🇳India—PythonPerlRTL design
- Senior Design Verification Engineer, AI HardwareTenstorrent · 🇷🇸Belgrade, Serbia—SeniorAIVerilogFirmware
- Staff Design Verification Engineer, AI HardwareTenstorrent · 🇷🇸Belgrade, Serbia—Lead and aboveAIFirmwareCompilers
- Physical Design Engineer, New GradSambaNova · 🇺🇸San Jose, California, United States$120K - $150KJuniorPythonPerlTest planning
- Design Verification Engineer, New GradSambaNova · 🇺🇸San Jose, California, United States$120K - $150KJuniorPythonVerilogPerl
- Junior Emulation EngineerCelero Communications, Inc. · 🇦🇷Cordoba, Argentina—JuniorPythonLinuxVerilog
- Technical Programme Manager, Electrical EngineeringIonQ · 🇺🇸College Park, Maryland, United States$152K - $228KJiraConfluenceSmartsheet
- Synthesis & STA Engineer – High-Speed SerDesAstera Labs · 🇺🇸San Jose, California, United States$160K - $200KPythonVerilogPerl
- Senior Design Verification EngineerAstera Labs · 🇺🇸San Jose, California, United States · +2 more locations$148K - $165KSeniorPythonVerilogPerl
- Senior Embedded Software EngineerPure Storage · 🇺🇸Santa Clara, California$202K - $248KSeniorPythonC++Linux
- Principal Verification EngineerAstera Labs · 🇺🇸San Jose, California, United States · +1 more location$185K - $230KLead and abovePythonC++Verilog
- Staff Engineer, RTL Design, AI HardwareTenstorrent · 🇷🇸Belgrade, Serbia—Lead and aboveAIVerilogCompilers
- Senior Engineer, RTL Design, AI HardwareTenstorrent · 🇷🇸Belgrade, Serbia—SeniorAIVerilogCompilers
- Director, Silicon Logical DesignGraphcore · 🇮🇳Bengaluru, India · +1 more location—Lead and aboveVerilogPerformance managementHardware interfaces
- Physical Design Engineering DirectorAstera Labs · 🇨🇦Toronto, Ontario, CanadaCA$200K - CA$250KLead and abovePythonPerlHardware interfaces
- Senior Staff/Principal Software Engineer - GPU System Software, Onboard ExecutionZoox · 🇺🇸Foster City, CA$339K - $455KLead and aboveC++LinuxCUDA
- Silicon Validation EngineerDensityAI · 🇺🇸Mountain View, CA$250K - $300KPythonC++Firmware
- Principal Physical Design EngineerAstera Labs · 🇮🇳Bengaluru, Karnataka, India · +3 more locations—Lead and abovePythonVerilogPerl
- Senior Digital ASIC Design Engineer - DSP/Analog/SerDesCelero Communications, Inc. · 🇨🇦Ottawa, Ontario, Canada · +2 more locations—SeniorPythonMATLABVerilog
- Research Engineer, Chip Design RLAnthropic · 🇺🇸San Francisco, CA$500K - $850KLLMReinforcement learningASIC
- Post-Silicon Validation Engineer (Multiple Levels)Celero Communications, Inc. · 🇺🇸🇨🇦Irvine, CA, or Ottawa, Ontario, CanadaCA$100K - CA$200KPythonLoad testingFirmware
- Staff SoC ArchitectGraphcore · 🇬🇧Bristol, UK—Lead and aboveASICRTL design
- Power Architect – AI SOCEnCharge AI · 🇮🇳India—PythonPerlFirmware
- Graduate SoC Architecture Engineer 2027Graphcore · 🇬🇧Bristol, UK—JuniorRustPythonC++
- Silicon Summer Intern 2027Graphcore · 🇬🇧Bristol, UK; Cambridge, UK—InternPythonC++ASIC
- Graduate Silicon Engineer 2027Graphcore · 🇬🇧Bristol, UK; Cambridge, UK—JuniorPythonC++ASIC
- Senior SoC ArchitectGraphcore · 🇬🇧Bristol, UK—SeniorASICRTL design
- Staff ML Accelerator ArchitectWaymo · 🇺🇸Mountain View, CA, USA; New York, New York, USA$251K - $310KLead and aboveMachine LearningVerilogCompilers
- Applied Researcher - Chip DesignPrimeIntellect · 🇺🇸San Francisco—PythonLangChainDatadog
- Senior Manager, Cryptographic EngineeringIonQ · 🇨🇭Geneva, Switzerland—SeniorEnglishGermanCryptography
- Associate Embedded Software EngineerAnysignal · 🇺🇸Los Angeles, CA$110K - $145KJuniorPythonC++Linux
- Director ASIC Technical Program ManagementAstera Labs · 🇺🇸San Jose, California, United States$210K - $275KLead and aboveFirmwareHardware interfacesASIC
- FPGA Engineer (Starshield)SpaceX · 🇺🇸Hawthorne, CA$125K - $160KPythonC++Bash
- SoC EngineerOpenAI · 🇺🇸San Francisco$287K - $485KHybridVerilogFirmwareHardware interfaces
- Embedded Software EngineerAnysignal · 🇺🇸Los Angeles, CA$130K - $165KPythonC++Linux
- Teach Lead Physical Design EngineerAstera Labs · 🇸🇬Singapore, Singapore—Lead and abovePythonPerlHardware interfaces
- Analog Mixed Signal Design EngineerAstera Labs · 🇸🇬Singapore, Singapore—PythonMATLABVerilog
- Tech Lead Analog Mixed-Signal IC Layout EngineerAstera Labs · 🇸🇬Singapore, Singapore—Lead and abovePythonC++Verilog
- Senior Analog Mixed-Signal IC Layout EngineerAstera Labs · 🇸🇬Singapore, Singapore—SeniorPythonC++Verilog
- Senior Software Engineer - Full Stack DevelopmentBlackStone eIT · 🇦🇪Dubai, Dubai, United Arab Emirates—SeniorReactNode.jsSQL
- Sr. ASIC Design Engineer (Silicon Engineering)SpaceX · 🇺🇸Palo Alto, CA · +3 more locations$175K - $280KSeniorPythonVerilogFirmware
- ASIC Design Engineer (Silicon Engineering)SpaceX · 🇺🇸Palo Alto, CA$135K - $175KPythonC++Bash
- Physical Design EngineerSK hynix memory solutions America Inc. · 🇺🇸San Jose—PythonMachine LearningPerl
- Senior ASIC RTL Design Engineer, AI HardwareCerebras · 🇺🇸Sunnyvale, CA$200K - $290KHybridSeniorPython.NETMachine Learning
- Digital ASIC Design EngineerAttoTude · 🇩🇪Nuremberg, Germany—PythonMATLABVerilog
- Datacenter & Agentic AI Workload Performance Optimization EngineerTenstorrent · 🇺🇸🇨🇦Santa Clara, California, United States; Toronto, Ontario…—RustGoPython
- Formal Verification EngineerTenstorrent · 🇺🇸🇪🇸Santa Clara, California, United States; Spain—PythonC++Verilog
- Research Scientist - Loop Engineering and AI InfrastructureSK hynix memory solutions America Inc. · 🇺🇸San Jose—PythonMachine LearningAI
- Datacenter & Agentic AI Workload Performance Analysis EngineerTenstorrent · 🇺🇸Santa Clara, California, United States—PythonC++Linux
- Senior Software Engineer in Test, UI PlatformOkta · 🇨🇦Toronto, Ontario, CanadaCA$118K - CA$162KSeniorTypeScriptJavaScriptMachine Learning
- Staff Cryptography EngineerIonQ · 🇨🇭Geneva, Switzerland—Lead and aboveRustPythonC++
- FPGA/ASIC Design Engineer (Silicon Engineering)SpaceX · 🇺🇸Irvine, CA · +1 more location$125K - $160KPythonC++Bash
- Tech Lead, Digital Design EngineerAstera Labs · 🇺🇸San Jose, California, United States$176K - $195KLead and abovePythonHardware interfacesASIC
- Technical Program Manager SOC & Digital DesignTenstorrent · 🇯🇵Tokyo, Japan—Machine LearningJapaneseCompilers
- Design Verification Emulation, HardwareRiver AI Inc. · 🇺🇸Austin, TX, Palo Alto, CA$200K - $420KPythonC++CI/CD
- Tech Lead Engineer, Design VerificationAstera Labs · 🇺🇸San Jose, California, United States$176K - $195KLead and abovePythonVerilogPowerShell
- Staff Engineer, Post-Silicon ValidationTenstorrent · 🇺🇸Austin, Texas, United States; Santa Clara, California, Un…—Lead and aboveLinuxFirmwareCompilers
- Physical Design ArchitectEnvision Employment Solutions · New Cairo City, Cairo Governorate, Egypt—ASICComputer architectureRTL design
Showing the newest 100. See all 367 in search
Who is hiring for RTL design roles
Where RTL design roles are
- 🇺🇸United States234
- 🇺🇸California186
- 🇺🇸San Francisco Bay Area146
- 🌏Asia-Pacific53
- 🇮🇳India43
- 🇪🇺Europe40
- 🇺🇸Austin, TX40
- 🇺🇸Texas40
- 🇮🇳Bangalore37
- 🇨🇦Canada26
A role that lists several places is counted in each of them.
What RTL design roles pay, by level
| Level in the title | Median advertised salary | Roles counted |
|---|---|---|
| No level in the title | $195K | 61 |
| Senior | $210K | 47 |
| Lead and above | $231K | 52 |
Medians of the midpoints of advertised yearly US-dollar ranges; a level needs at least 15 such roles. Advertised, not verified pay.
Jobs you can get with RTL design
| Kind of work | Open jobs asking for RTL design | Median advertised pay |
|---|---|---|
| Hardware engineer | 254 | $212K |
| ASIC and chip design engineer | 176 | $220K |
| Design verification engineer | 68 | $210K |
| Test and validation engineer | 63 | $210K |
| FPGA engineer | 31 | $172K |
| Architect (software and systems) | 25 | $240K |
| Electrical engineer | 15 | $190K |
| Analog and mixed-signal engineer | 12 | $190K |
Skills asked together with RTL design
Python (68%), ASIC (66%), Verilog (44%), Hardware interfaces (42%), SystemVerilog (41%), Firmware (36%), Perl (28%), Computer architecture (27%) of the 367 open postings that name RTL design.
Companies hiring for RTL design
RTL design salariesQuestions about RTL design jobs
- What is RTL design?
- Describing a chip’s logic in code before it becomes a physical design. 367 open roles on Jobs Every Hour ask for it as of Nov 15, 2026.
- How many RTL design jobs are open right now?
- There are 367 open RTL design jobs at 42 companies on Jobs Every Hour as of Nov 15, 2026. 16 of them were posted in the last seven days. The list is rebuilt every hour from the employers' own careers pages.
- Which companies have the most RTL design jobs?
- Right now the most openings are at Astera Labs (73), Tenstorrent (52), SpaceX (29), Graphcore (23) and K2 Space (17). The ranking changes as companies open and close roles.
- Are there remote RTL design jobs?
- 14 of the 367 open RTL design jobs (4%) are listed as remote. Remote roles are often limited to certain countries or time zones, so check the location line of each job.
- What do RTL design jobs pay?
- The median advertised salary is $212K, based on 163 open roles that publish a yearly US-dollar range. The middle half of those roles advertise between $172K and $242K. These are advertised ranges, not verified pay. Most employers here are technology companies, so the figures run above the wider market for the same work.
- Is it hard to get an RTL design job?
- 10 of the 367 open RTL design jobs (3%) are for beginners: junior roles and internships. Of the 248 postings that state experience, the median asks for 6 years. 42 companies are hiring and 16 roles were posted in the last seven days. Matching your resume to the skills each posting names helps most; the free resume builder shows the match.
- How is AI changing RTL design jobs?
- 74 of the 367 open RTL design jobs (20%) ask for AI or machine-learning skills, most often Machine Learning, AI, Computer Vision. Employers still list 367 such roles today at 42 companies. Counted from the postings' own text on Nov 15, 2026.
- What skills do RTL design jobs ask for?
- Most often RTL design (100%), Python (68%), ASIC (66%), Verilog (44%), Hardware interfaces (42%) of the 367 open postings, counted from their own text on Nov 15, 2026.
- Which job titles come up most in RTL design jobs?
- Physical Design Engineer (16), Design Verification Engineer (10), Principal Physical Design Engineer (8), FPGA Engineer (7), Principal DFT Engineer (7): the most common titles among the 367 open roles, without the level and place notes in brackets.
- Are RTL design jobs in demand in 2026?
- 367 RTL design jobs are open on Jobs Every Hour today at 42 companies, 0.2% of all 148,162 open jobs here; 16 were posted in the last seven days. The median advertised salary is $212K. 14 (4%) can be done remotely.
- How do I apply for RTL design jobs?
- Open a job and press “Apply on company site”. You go straight to the employer's own careers page and apply there. Jobs Every Hour needs no account and charges nothing for applying.
Narrow down RTL design jobs
By place
- RTL design jobs in the United States 234
- RTL design jobs in California 186
- RTL design jobs in San Francisco Bay Area 146
- 🌏RTL design jobs in Asia-Pacific 53
- RTL design jobs in India 43
- RTL design jobs in Europe 40
- RTL design jobs in Austin, TX 40
- RTL design jobs in Texas 40
- RTL design jobs in Bangalore 37
- RTL design jobs in Canada 26
- RTL design jobs in Israel 22
- RTL design jobs in Toronto 22
- RTL design jobs in Los Angeles, CA 19
- RTL design jobs in Tel Aviv 13
- RTL design jobs in the United Kingdom 12
- RTL design jobs in Seattle, WA 12



















