ASIC and chip design engineer jobs
ASIC and chip design engineer: a person in this job designs the logic and layout of computer chips, from processors to AI accelerators. Astera Labs, SpaceX, Tenstorrent, K2 Space and Graphcore have the most open roles with “ASIC and chip design engineer” or a close variant in the title right now.
288 open roles · 12 posted in the last 7 days · 10% remote · 50 companies hiring · $218K median advertised salary · checked Nov 15 against employer career pages
| Period | Count |
|---|---|
| under $75K | 0 |
| $75K to $100K | 0 |
| $100K to $125K | 3 |
| $125K to $150K | 10 |
| $150K to $175K | 7 |
| $175K to $200K | 5 |
| $200K to $250K | 82 |
| $250K to $300K | 11 |
| $300K and more | 18 |
Skills asked for in ASIC and chip design engineer roles
Bars show the share of these 288 roles; one role can count in several rows.
Newest ASIC and chip design engineer jobs
- Advanced ASIC FPGA Verification EngineerM9 Solutions · Remote - No clearance required$100K - $115KRemotePythonLinuxVerilog
- Physical Design, Intern (Summer 2027)Lightmatter · 🇺🇸Boston, MA—InternPythonData centersHigh-performance computing
- Senior ASIC Package Design EngineerK2 Space · 🇺🇸United States - Remote · +1 more location$180K - $260KRemoteSeniorAnalog designASIC
- Senior ASIC Physical Design EngineerK2 Space · 🇺🇸United States - Remote · +1 more location$170K - $250KRemoteSeniorAnalog designCompilersASIC
- Senior ASIC Design Verification EngineerK2 Space · 🇺🇸United States - Remote · +1 more location$170K - $250KRemoteSeniorPythonC++CI/CD
- Principal ASIC Physical Design EngineerK2 Space · 🇺🇸United States - Remote · +2 more locations$190K - $280KRemoteLead and aboveAnalog designASICRTL design
- Principal ASIC Package Design EngineerK2 Space · 🇺🇸United States - Remote · +1 more location$200K - $280KRemoteLead and aboveContract negotiationAnalog designASIC
- Principal ASIC Design Verification EngineerK2 Space · 🇺🇸United States - Remote · +1 more location$190K - $285KRemoteLead and abovePythonC++CI/CD
- Principal ASIC Synthesis and Timing EngineerK2 Space · 🇺🇸United States - Remote$190K - $280KRemoteLead and aboveAnalog designASICRTL design
- Sr. Physical Design Flow & Methodology EngineerLightmatter · 🇺🇸Boston, MA$154K - $175KSeniorPythonLLMCI/CD
- Staff Engineer, Digital ASIC Design — Storage ControllersSK hynix memory solutions America Inc. · 🇺🇸San Jose—Lead and aboveMachine LearningVerilogStorage systems
- RTL Design Engineer, Networking / NoCOpenAI · 🇺🇸San Francisco$287K - $485KHybridVerilogHigh-performance computingASIC
- Physical Design and CAD EngineerAstera Labs · 🇺🇸San Jose, California, United States$160K - $200KPythonHardware interfacesCompilers
- DFT EngineerTenstorrent · 🇺🇸Austin, Texas, United States; Fort Collins, Colorado, Uni… · +1 more location—VerilogHardware interfacesCompilers
- Principal ASIC EngineerEchodyne Corp · 🇺🇸Kirkland, WA$165K - $247KLead and above
- Physical Design and Verification EngineerNeuralink · 🇺🇸South San Francisco, California, United States$131K - $265KPython
- Senior Microarchitecture ResearcherIonQ · 🇺🇸Bothell, Washington, United States; Boulder, Colorado, Un…$188K - $282KSeniorTechnical writingFinancial modelingRTL design
- Silicon Design LeadOpenAI · 🇺🇸San Francisco$287K - $485KHybridLead and aboveVerilogThreat modelingFirmware
- Principal PCS/PMA RTL Design EngineerAstera Labs · 🇺🇸San Jose, California, United States$185K - $240KLead and abovePythonVerilogPerl
- Staff Engineer, DFTAmbiq Micro, Inc. · 🇺🇸Austin, Texas, United States—Lead and above
- Principal Physical Design CAD EngineerAstera Labs · 🇮🇱Tel Aviv-Yafo, Tel Aviv District, Israel · +1 more location—Lead and abovePythonLLMCI/CD
- Staff/ Principal Physical Design STA EngineerAstera Labs · 🇮🇱Haifa District, Israel · +1 more location—Lead and abovePythonPerlData centers
- Staff / Principal ASIC Design EngineerAstera Labs · 🇮🇱Haifa District, Israel · +1 more location—Lead and abovePythonVerilogPerl
- DFT EngineerAstera Labs · 🇮🇱Haifa District, Israel · +2 more locations—PythonPerlVideo editing
- Staff DFT EngineerAstera Labs · 🇮🇱Haifa District, Israel · +1 more location—Lead and abovePythonPerlVideo editing
- Principal DFT EngineerAstera Labs · 🇮🇱Haifa District, Israel · +2 more locations—Lead and abovePythonPerlHardware interfaces
- Staff Physical Design Engineer - SoC EMIR EngineerAstera Labs · 🇮🇱Haifa District, Israel · +1 more location—Lead and aboveHardware interfacesCompilersFEA
- Senior/ Staff Physical Design EngineerAstera Labs · 🇮🇱Tel Aviv-Yafo, Tel Aviv District, Israel · +1 more location—Lead and abovePythonHardware interfacesCompilers
- Physical Design Team LeadAstera Labs · 🇮🇱Haifa District, Israel · +1 more location—Lead and abovePythonPerlHardware interfaces
- Staff/ Principal Chip Top Physical Design EngineerAstera Labs · 🇮🇱Haifa District, Israel · +1 more location—Lead and aboveHardware interfacesCompilersASIC
- Senior ASIC Design EngineerAstera Labs · 🇮🇱Haifa District, Israel · +1 more location—SeniorPythonVerilogPerl
- Hardware Engineers: RTL Implementation and Evaluation WorkflowsTerac · 🇺🇸United States—RemoteVerilogHardware testingASIC
- Principal SoC RTL EngineerAmbiq Micro, Inc. · 🇺🇸Austin, Texas, United States—Lead and aboveVerilog
- Director of Physical DesignAmbiq Micro, Inc. · 🇺🇸Austin, Texas, United States—Lead and above
- ASIC ArchitectDelos Data · 🇺🇸Palo Alto$160K - $280KHybridPythonC++Verilog
- STA/Timing Closure LeadAlpha Design Ai Inc · 🇺🇸San Jose—Lead and abovePython
- RTL LeadNormalComputing · 🇺🇸Mountain View$274K - $350KHybridLead and aboveVerilog
- SoC Clocking Specialist (Physical Design)EnCharge AI · 🇮🇳India—PythonPerlRTL design
- Post-Silicon Validation Engineer, New GradSambaNova · 🇺🇸San Jose, California, United States$120K - $150KJuniorPythonC++Bash
- Physical Design Engineer, New GradSambaNova · 🇺🇸San Jose, California, United States$120K - $150KJuniorPythonPerlTest planning
- Staff Engineer, RTL Design, AI HardwareTenstorrent · 🇷🇸Belgrade, Serbia—Lead and aboveAIVerilogCompilers
- Senior Engineer, RTL Design, AI HardwareTenstorrent · 🇷🇸Belgrade, Serbia—SeniorAIVerilogCompilers
- Physical Design Engineering DirectorAstera Labs · 🇨🇦Toronto, Ontario, CanadaCA$200K - CA$250KLead and abovePythonPerlHardware interfaces
- Sr. IC Package Design Engineer (Silicon Engineering)SpaceX · 🇺🇸Austin, TX · +1 more location—SeniorFirmwareAnalog designASIC
- Silicon Validation EngineerDensityAI · 🇺🇸Mountain View, CA$250K - $300KPythonC++Firmware
- Principal Physical Design EngineerAstera Labs · 🇮🇳Bengaluru, Karnataka, India · +3 more locations—Lead and abovePythonVerilogPerl
- Hardware Engineer, DFTNormalComputing · 🇺🇸Mountain View$232K - $304KHybridPython
- Senior Digital ASIC Design Engineer - DSP/Analog/SerDesCelero Communications, Inc. · 🇨🇦Ottawa, Ontario, Canada · +2 more locations—SeniorPythonMATLABVerilog
- Research Engineer, Chip Design RLAnthropic · 🇺🇸San Francisco, CA$500K - $850KLLMReinforcement learningASIC
- Post-Silicon Validation Engineer (Multiple Levels)Celero Communications, Inc. · 🇺🇸🇨🇦Irvine, CA, or Ottawa, Ontario, CanadaCA$100K - CA$200KPythonLoad testingFirmware
- Staff SoC ArchitectGraphcore · 🇬🇧Bristol, UK—Lead and aboveASICRTL design
- Physical Design LeadNormalComputing · 🇺🇸Mountain View$200K - $400KHybridLead and abovePython
- Principal Post-Silicon Validation EngineerAstera Labs · 🇺🇸San Jose, California, United States$207K - $230KLead and abovePythonC++C
- RTL Design EngineerDelos Data · 🇺🇸Palo Alto$160K - $240KRemotePythonVerilog
- Graduate SoC Architecture Engineer 2027Graphcore · 🇬🇧Bristol, UK—JuniorRustPythonC++
- Graduate Silicon Engineer 2027Graphcore · 🇬🇧Bristol, UK; Cambridge, UK—JuniorPythonC++ASIC
- Senior SoC ArchitectGraphcore · 🇬🇧Bristol, UK—SeniorASICRTL design
- Microarchitect and RTL Designer - ComputeMatx · 🇺🇸Mountain View (HQ) or Remote$175K - $400KRemotePythonC++Verilog
- Staff ML Accelerator ArchitectWaymo · 🇺🇸Mountain View, CA, USA; New York, New York, USA$251K - $310KLead and aboveMachine LearningVerilogCompilers
- Post-Silicon Validation EngineerVoltai.careers · 🇺🇸Palo Alto Office—PythonC++
- Design for Test (DFT) EngineerVoltai.careers · 🇺🇸Palo Alto Office—Python
- Physical Design EngineerVoltai.careers · 🇺🇸Palo Alto Office—PythonMachine Learning
- RTL Design EngineerVoltai.careers · 🇺🇸Palo Alto Office—PythonVerilog
- Chip ArchitectVoltai.careers · 🇺🇸Palo Alto Office—PythonC++
- Applied Researcher - Chip DesignPrimeIntellect · 🇺🇸San Francisco—PythonLangChainDatadog
- Hardware Engineer, Physical DesignNormalComputing · 🇺🇸Mountain View$200K - $400KHybridPython
- ASIC ArchitectNormalComputing · 🇺🇸Mountain View$200K - $400KHybridPythonC++LLM
- Director ASIC Technical Program ManagementAstera Labs · 🇺🇸San Jose, California, United States$210K - $275KLead and aboveFirmwareHardware interfacesASIC
- DFT EngineerRicursive Intelligence · 🇺🇸Palo Alto—PythonVerilog
- Teach Lead Physical Design EngineerAstera Labs · 🇸🇬Singapore, Singapore—Lead and abovePythonPerlHardware interfaces
- Sr. ASIC Design Engineer (Silicon Engineering)SpaceX · 🇺🇸Palo Alto, CA · +3 more locations$175K - $280KSeniorPythonVerilogFirmware
- ASIC Design Engineer (Silicon Engineering)SpaceX · 🇺🇸Palo Alto, CA$135K - $175KPythonC++Bash
- Principal ASIC Verification EngineerAtomcomputing · 🇺🇸Austin, TX$180K - $220KLead and abovePythonLinuxVerilog
- Director, Post-Silicon Validation (Functional)Graphcore · 🇺🇸Austin, Texas, United States—Lead and abovePythonC++Linux
- Physical Design LeadPhinitylabs · 🇺🇸San Francisco—Lead and above
- Physical Design EngineerSK hynix memory solutions America Inc. · 🇺🇸San Jose—PythonMachine LearningPerl
- Senior ASIC RTL Design Engineer, AI HardwareCerebras · 🇺🇸Sunnyvale, CA$200K - $290KHybridSeniorPython.NETMachine Learning
- Digital ASIC Design EngineerAttoTude · 🇩🇪Nuremberg, Germany—PythonMATLABVerilog
- Senior SoC Architect (f/m/d)Blacksemiconductor · 🇺🇸United States—RemoteSeniorPythonC++
- DFT InternAmbiq Micro, Inc. · 🇸🇬Singapore—InternPythonLinuxVerilog
- FPGA/ASIC Design Engineer (Silicon Engineering)SpaceX · 🇺🇸Irvine, CA · +1 more location$125K - $160KPythonC++Bash
- Post-Silicon Lab ManagerTenstorrent · 🇺🇸Santa Clara, California, United States—JiraConfluenceHardware interfaces
- Staff Engineer, Post-Silicon ValidationTenstorrent · 🇺🇸Austin, Texas, United States; Santa Clara, California, Un…—Lead and aboveLinuxFirmwareCompilers
- DFT Architect (Physical Design & Chiplet)Envision Employment Solutions · New Cairo City, Cairo Governorate, Egypt—PythonPerlHardware interfaces
- Physical Design ArchitectEnvision Employment Solutions · New Cairo City, Cairo Governorate, Egypt—ASICComputer architectureRTL design
- Physical Design SiP ArchitectEnvision Employment Solutions · New Cairo City, Cairo Governorate, Egypt—
- Senior RTL Design EngineerEnvision Employment Solutions · New Cairo City, Cairo Governorate, Egypt—SeniorPythonVerilogPerl
- Sr. Staff / Principal Physical Design EngineerSK hynix memory solutions America Inc. · 🇺🇸San Jose—Lead and abovePythonMachine LearningPerl
- Senior DFT EngineerEnvision Employment Solutions · New Cairo City, Cairo Governorate, Egypt—SeniorPythonPerlHardware interfaces
- Senior Physical Design Engineer (Floorplan & PnR)Envision Employment Solutions · New Cairo City, Cairo Governorate, Egypt—SeniorPythonPerlRF engineering
- Senior Physical Design Engineer (Synthesis, SDC & STA)Envision Employment Solutions · New Cairo City, Cairo Governorate, Egypt—SeniorPythonPerlCompilers
- VLSI Functional Safety Hardware ArchitectEnvision Employment Solutions · New Cairo City, Cairo Governorate, Egypt—VerilogPCB designASIC
- DFT EngineerDelos Data · 🇺🇸Palo Alto$160K - $260KRemotePythonVerilog
- SOC Integration EngineerMatx · 🇺🇸Mountain View$160K - $275KHybridPythonVerilogPerl
- Physical Design Engineer, TimingTenstorrent · 🇺🇸Austin, Texas, United States; Fort Collins, Colorado, Uni…—PythonPerlCompilers
- Silicon Design ArchitectAstera Labs · 🇮🇳Bengaluru, Karnataka, India—FirmwareHardware interfacesASIC
- Senior Mixed-Signal Post-Silicon Validation EngineerK2 Space · 🇺🇸Seattle, WA · +1 more location$170K - $250KSeniorPythonFirmwareHardware testing
- Principal Physical Design EngineerCelero Communications, Inc. · 🇺🇸San Jose, CA · +1 more location$150K - $250KLead and abovePythonPerlAnalog design
- Senior RF/mmWave Post-Silicon Validation EngineerK2 Space · 🇺🇸Seattle, WA · +1 more location$170K - $250KSeniorPythonEthereumFirmware
- Senior Serdes Characterization & Post-Silicon Validation EngineerK2 Space · 🇺🇸Seattle, WA · +1 more location$170K - $250KSeniorPythonAmplitudeLoad testing
Showing the newest 100 of 228. The search looks through all of them by title, place and pay.
Who is hiring for ASIC and chip design engineer roles
Where ASIC and chip design engineer roles are
- 🇺🇸United States204
- 🇺🇸California139
- 🇺🇸San Francisco Bay Area116
- 🇺🇸Texas42
- 🇺🇸Austin, TX41
- 🌏Asia-Pacific25
- 🇮🇱Israel24
- 🇪🇺Europe21
- 🇺🇸Los Angeles, CA20
- 🇮🇳India18
A role that lists several places is counted in each of them.
What ASIC and chip design engineer roles pay, by level
| Level in the title | Median advertised salary | Roles counted |
|---|---|---|
| No level in the title | $218K | 52 |
| Senior | $210K | 35 |
| Lead and above | $235K | 45 |
Medians of the midpoints of advertised yearly US-dollar ranges; a level needs at least 15 such roles. Advertised, not verified pay.
Kinds of work close to this one
Roles where employers ask for the same skills. The bar shows how much the skill lists overlap; the text names the shared skills and, where 30 postings state pay, the median advertised pay there.
Companies hiring chip design engineers
ASIC and chip design engineer salaryQuestions about ASIC and chip design engineer jobs
- What is an ASIC and chip design engineer job?
- In an ASIC and chip design engineer job, a person designs the logic and layout of computer chips, from processors to AI accelerators. 288 such roles are open on Jobs Every Hour as of Nov 15, 2026.
- How many ASIC and chip design engineer jobs are open right now?
- There are 288 open ASIC and chip design engineer jobs at 50 companies on Jobs Every Hour as of Nov 15, 2026. 12 of them were posted in the last seven days. The list is rebuilt every hour from the employers' own careers pages.
- Which companies have the most ASIC and chip design engineer jobs?
- Right now the most openings are at Astera Labs (51), SpaceX (40), Tenstorrent (26), K2 Space (22) and Graphcore (10). The ranking changes as companies open and close roles.
- Are there remote ASIC and chip design engineer jobs?
- 30 of the 288 open ASIC and chip design engineer jobs (10%) are listed as remote. Remote roles are often limited to certain countries or time zones, so check the location line of each job.
- What do ASIC and chip design engineer jobs pay?
- The median advertised salary is $218K, based on 136 open roles that publish a yearly US-dollar range. The middle half of those roles advertise between $210K and $245K. These are advertised ranges, not verified pay. Most employers here are technology companies, so the figures run above the wider market for the same work.
- Is it hard to get an ASIC and chip design engineer job?
- 10 of the 288 open ASIC and chip design engineer jobs (3%) are for beginners: junior roles and internships. Of the 200 postings that state experience, the median asks for 6 years. 50 companies are hiring and 12 roles were posted in the last seven days. Matching your resume to the skills each posting names helps most; the free resume builder shows the match.
- How is AI changing ASIC and chip design engineer jobs?
- 43 of the 288 open ASIC and chip design engineer jobs (15%) ask for AI or machine-learning skills, most often Machine Learning, LLM, AI. Employers still list 288 such roles today at 50 companies. Counted from the postings' own text on Nov 15, 2026.
- What skills do ASIC and chip design engineer jobs ask for?
- Most often Python (67%), ASIC (66%), RTL design (61%), Hardware interfaces (32%), Verilog (31%) of the 288 open postings, counted from their own text on Nov 15, 2026.
- Which job titles come up most in ASIC and chip design engineer jobs?
- Physical Design Engineer (19), DFT Engineer (8), Principal DFT Engineer (8), Principal Physical Design Engineer (8), Staff Engineer (6): the most common titles among the 288 open roles, without the level and place notes in brackets.
- Are ASIC and chip design engineer jobs in demand in 2026?
- 288 ASIC and chip design engineer jobs are open on Jobs Every Hour today at 50 companies, 0.2% of all 148,162 open jobs here; 12 were posted in the last seven days. The median advertised salary is $218K. 30 (10%) can be done remotely.
- How do I apply for ASIC and chip design engineer jobs?
- Open a job and press “Apply on company site”. You go straight to the employer's own careers page and apply there. Jobs Every Hour needs no account and charges nothing for applying.
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