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ASIC and chip design engineer jobs in San Francisco Bay Area
116 open roles for chip design engineers in San Francisco Bay Area as of Nov 15, 2026. Tenstorrent, SpaceX, Astera Labs, SambaNova and Matx have the most. 12 are remote and the median advertised salary is $228K.
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Skills asked for in ASIC and chip design engineer roles in San Francisco Bay Area
Bars show the share of these 116 roles; one role can count in several rows.
- Staff Engineer, Digital ASIC Design — Storage ControllersSK hynix memory solutions America Inc. · 🇺🇸San Jose—Lead and aboveMachine LearningVerilogStorage systems
- RTL Design Engineer, Networking / NoCOpenAI · 🇺🇸San Francisco$287K - $485KHybridVerilogHigh-performance computingASIC
- Physical Design and CAD EngineerAstera Labs · 🇺🇸San Jose, California, United States$160K - $200KPythonHardware interfacesCompilers
- DFT EngineerTenstorrent · 🇺🇸Austin, Texas, United States; Fort Collins, Colorado, Uni… · +1 more location—VerilogHardware interfacesCompilers
- Physical Design and Verification EngineerNeuralink · 🇺🇸South San Francisco, California, United States$131K - $265KPython
- Silicon Design LeadOpenAI · 🇺🇸San Francisco$287K - $485KHybridLead and aboveVerilogThreat modelingFirmware
- Principal PCS/PMA RTL Design EngineerAstera Labs · 🇺🇸San Jose, California, United States$185K - $240KLead and abovePythonVerilogPerl
- ASIC ArchitectDelos Data · 🇺🇸Palo Alto$160K - $280KHybridPythonC++Verilog
- STA/Timing Closure LeadAlpha Design Ai Inc · 🇺🇸San Jose—Lead and abovePython
- RTL LeadNormalComputing · 🇺🇸Mountain View$274K - $350KHybridLead and aboveVerilog
- Post-Silicon Validation Engineer, New GradSambaNova · 🇺🇸San Jose, California, United States$120K - $150KJuniorPythonC++Bash
- Physical Design Engineer, New GradSambaNova · 🇺🇸San Jose, California, United States$120K - $150KJuniorPythonPerlTest planning
- Silicon Validation EngineerDensityAI · 🇺🇸Mountain View, CA$250K - $300KPythonC++Firmware
- Hardware Engineer, DFTNormalComputing · 🇺🇸Mountain View$232K - $304KHybridPython
- Senior Digital ASIC Design Engineer - DSP/Analog/SerDesCelero Communications, Inc. · 🇺🇸San Jose, CA$150K - $250KSeniorPythonMATLABVerilog
- Research Engineer, Chip Design RLAnthropic · 🇺🇸San Francisco, CA$500K - $850KLLMReinforcement learningASIC
- Physical Design LeadNormalComputing · 🇺🇸Mountain View$200K - $400KHybridLead and abovePython
- Principal Post-Silicon Validation EngineerAstera Labs · 🇺🇸San Jose, California, United States$207K - $230KLead and abovePythonC++C
- RTL Design EngineerDelos Data · 🇺🇸Palo Alto$160K - $240KRemotePythonVerilog
- Microarchitect and RTL Designer - ComputeMatx · 🇺🇸Mountain View (HQ) or Remote$175K - $400KRemotePythonC++Verilog
- Staff ML Accelerator ArchitectWaymo · 🇺🇸Mountain View, CA, USA; New York, New York, USA$251K - $310KLead and aboveMachine LearningVerilogCompilers
- Post-Silicon Validation EngineerVoltai.careers · 🇺🇸Palo Alto Office—PythonC++
- Design for Test (DFT) EngineerVoltai.careers · 🇺🇸Palo Alto Office—Python
- Physical Design EngineerVoltai.careers · 🇺🇸Palo Alto Office—PythonMachine Learning
- RTL Design EngineerVoltai.careers · 🇺🇸Palo Alto Office—PythonVerilog
- Chip ArchitectVoltai.careers · 🇺🇸Palo Alto Office—PythonC++
- Applied Researcher - Chip DesignPrimeIntellect · 🇺🇸San Francisco—PythonLangChainDatadog
- Hardware Engineer, Physical DesignNormalComputing · 🇺🇸Mountain View$200K - $400KHybridPython
- ASIC ArchitectNormalComputing · 🇺🇸Mountain View$200K - $400KHybridPythonC++LLM
- Director ASIC Technical Program ManagementAstera Labs · 🇺🇸San Jose, California, United States$210K - $275KLead and aboveFirmwareHardware interfacesASIC
- DFT EngineerRicursive Intelligence · 🇺🇸Palo Alto—PythonVerilog
- Sr. ASIC Design Engineer (Silicon Engineering)SpaceX · 🇺🇸Palo Alto, CA$175K - $280KSeniorPythonVerilogFirmware
- ASIC Design Engineer (Silicon Engineering)SpaceX · 🇺🇸Palo Alto, CA$135K - $175KPythonC++Bash
- Physical Design LeadPhinitylabs · 🇺🇸San Francisco—Lead and above
- Physical Design EngineerSK hynix memory solutions America Inc. · 🇺🇸San Jose—PythonMachine LearningPerl
- Senior ASIC RTL Design Engineer, AI HardwareCerebras · 🇺🇸Sunnyvale, CA$200K - $290KHybridSeniorPython.NETMachine Learning
- Post-Silicon Lab ManagerTenstorrent · 🇺🇸Santa Clara, California, United States—JiraConfluenceHardware interfaces
- Staff Engineer, Post-Silicon ValidationTenstorrent · 🇺🇸Austin, Texas, United States; Santa Clara, California, Un…—Lead and aboveLinuxFirmwareCompilers
- Sr. Staff / Principal Physical Design EngineerSK hynix memory solutions America Inc. · 🇺🇸San Jose—Lead and abovePythonMachine LearningPerl
- DFT EngineerDelos Data · 🇺🇸Palo Alto$160K - $260KRemotePythonVerilog
- SOC Integration EngineerMatx · 🇺🇸Mountain View$160K - $275KHybridPythonVerilogPerl
- Physical Design Engineer, TimingTenstorrent · 🇺🇸Austin, Texas, United States; Fort Collins, Colorado, Uni…—PythonPerlCompilers
- Principal Physical Design EngineerCelero Communications, Inc. · 🇺🇸San Jose, CA$150K - $250KLead and abovePythonPerlAnalog design
- Physical Design EngineerOpenAI · 🇺🇸San Francisco$225K - $485KPythonBazelHigh-performance computing
- Principal RTL Design Engineer, IO & Memory SystemsSambaNova · 🇺🇸Austin, Texas, United States; San Jose, California, Unite…$180K - $255KLead and aboveMachine LearningVerilogFirmware
- Principal Engineer, SoC NPU ArchitectSamsung Research America · 🇺🇸665 Clyde Avenue, Mountain View, CA, USA$242K - $377KLead and abovePythonC++Machine Learning
- Research Engineer, AI for Chip DesignOpenAI · 🇺🇸San Francisco$380K - $500KHybridAIVerilogLLM evaluation
- Physical Design Engineer (Silicon Engineering)SpaceX · 🇺🇸Palo Alto, CA$135K - $175KPythonBashPerl
- Physical Design EngineerDelos Data · 🇺🇸Palo Alto$180K - $240KRemotePythonPerl
- Physical Design CPU Methodology EngineerTenstorrent · 🇺🇸Santa Clara, California, United States—PythonPerlCompilers
Showing the newest 50. See all 116 in search
Who is hiring for ASIC and chip design engineer roles in San Francisco Bay Area
Where ASIC and chip design engineer roles in San Francisco Bay Area are
- 🇺🇸United States116
- 🇺🇸San Francisco Bay Area116
- 🇺🇸California116
- 🇺🇸Austin, TX17
- 🇺🇸Texas17
- 🇨🇦Canada2
- 🇪🇺Europe1
- 🇪🇸Spain1
- 🇨🇦Toronto1
- 🇺🇸New York, NY1
A role that lists several places is counted in each of them.
What ASIC and chip design engineer roles in San Francisco Bay Area pay, by level
| Level in the title | Median advertised salary | Roles counted |
|---|---|---|
| No level in the title | $222K | 42 |
| Lead and above | $244K | 28 |
Medians of the midpoints of advertised yearly US-dollar ranges; a level needs at least 15 such roles. Advertised, not verified pay.
Questions about ASIC and chip design engineer jobs in San Francisco Bay Area
- How many ASIC and chip design engineer jobs in San Francisco Bay Area are open right now?
- There are 116 open ASIC and chip design engineer jobs in San Francisco Bay Area at 27 companies on Jobs Every Hour as of Nov 15, 2026. 2 of them were posted in the last seven days. The list is rebuilt every hour from the employers' own careers pages.
- Which companies have the most ASIC and chip design engineer jobs in San Francisco Bay Area?
- Right now the most openings are at Tenstorrent (16), Astera Labs (11), SpaceX (11), SambaNova (9) and Matx (9). The ranking changes as companies open and close roles.
- Are there remote ASIC and chip design engineer jobs in San Francisco Bay Area?
- 12 of the 116 open ASIC and chip design engineer jobs in San Francisco Bay Area (10%) are listed as remote. Remote roles are often limited to certain countries or time zones, so check the location line of each job.
- What do ASIC and chip design engineer jobs in San Francisco Bay Area pay?
- The median advertised salary is $228K, based on 80 open roles that publish a yearly US-dollar range. The middle half of those roles advertise between $216K and $288K. These are advertised ranges, not verified pay. Most employers here are technology companies, so the figures run above the wider market for the same work.
- Is it hard to get one of the ASIC and chip design engineer jobs in San Francisco Bay Area?
- 2 of the 116 open ASIC and chip design engineer jobs in San Francisco Bay Area (2%) are for beginners: junior roles and internships. Of the 81 postings that state experience, the median asks for 7 years. 27 companies are hiring and 2 roles were posted in the last seven days. Matching your resume to the skills each posting names helps most; the free resume builder shows the match.
- How is AI changing ASIC and chip design engineer jobs in San Francisco Bay Area?
- 26 of the 116 open ASIC and chip design engineer jobs in San Francisco Bay Area (22%) ask for AI or machine-learning skills, most often Machine Learning, LLM, AI. Employers still list 116 such roles today at 27 companies. Counted from the postings' own text on Nov 15, 2026.
- What skills do ASIC and chip design engineer jobs in San Francisco Bay Area ask for?
- Most often Python (70%), ASIC (58%), RTL design (57%), Verilog (37%), Hardware interfaces (28%) of the 116 open postings, counted from their own text on Nov 15, 2026.
- Which job titles come up most in ASIC and chip design engineer jobs in San Francisco Bay Area?
- Physical Design Engineer (12), RTL Design Engineer (4), DFT Engineer (4), Staff Engineer (3), Post (3): the most common titles among the 116 open roles, without the level and place notes in brackets.
- Are ASIC and chip design engineer jobs in San Francisco Bay Area in demand in 2026?
- 116 ASIC and chip design engineer jobs in San Francisco Bay Area are open on Jobs Every Hour today at 27 companies, 0.1% of all 148,162 open jobs here; 2 were posted in the last seven days. The median advertised salary is $228K. 12 (10%) can be done remotely.
- How do I apply for ASIC and chip design engineer jobs in San Francisco Bay Area?
- Open a job and press “Apply on company site”. You go straight to the employer's own careers page and apply there. Jobs Every Hour needs no account and charges nothing for applying.