Design for Test (DFT) Engineer is open at Voltai.careers in Palo Alto Office. The posting gives no salary; similar roles in the United States advertise a median of $190K. Posted on Oct 19, 2026, and still on Voltai.careers’s careers page when we last checked, on Nov 15, 2026.
About the role
Define DFT architecture for SoCs and IP, including scan, compression, MBIST, LBIST, and boundary scan. - Insert and verify DFT logic, and generate ATPG patterns that meet coverage targets. - Work with RTL, synthesis, and physical design teams to close DFT timing and area impact. - Support silicon bring-up, pattern debug, and yield analysis with test and product engineering. - Build automation for DFT flows and…
The opening lines of the posting. The rest is on Voltai.careers’s careers page.
Hiring at Voltai.careers
Voltai.careers has 33 open roles right now, 2 of them remote. Most are in Engineering, Operations and Data & Research. See all its roles
