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ASIC and chip design engineer jobs in the United States
204 open roles for chip design engineers in the United States as of Nov 15, 2026. SpaceX, K2 Space, Tenstorrent, Astera Labs and SambaNova have the most. 27 are remote and the median advertised salary is $218K.
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Skills asked for in ASIC and chip design engineer roles in the United States
Bars show the share of these 204 roles; one role can count in several rows.
- Physical Design, Intern (Summer 2027)Lightmatter · 🇺🇸Boston, MA—InternPythonData centersHigh-performance computing
- Senior ASIC Package Design EngineerK2 Space · 🇺🇸United States - Remote · +1 more location$180K - $260KRemoteSeniorAnalog designASIC
- Senior ASIC Physical Design EngineerK2 Space · 🇺🇸United States - Remote · +1 more location$170K - $250KRemoteSeniorAnalog designCompilersASIC
- Senior ASIC Design Verification EngineerK2 Space · 🇺🇸United States - Remote · +1 more location$170K - $250KRemoteSeniorPythonC++CI/CD
- Principal ASIC Physical Design EngineerK2 Space · 🇺🇸United States - Remote · +2 more locations$190K - $280KRemoteLead and aboveAnalog designASICRTL design
- Principal ASIC Package Design EngineerK2 Space · 🇺🇸United States - Remote · +1 more location$200K - $280KRemoteLead and aboveContract negotiationAnalog designASIC
- Principal ASIC Design Verification EngineerK2 Space · 🇺🇸United States - Remote · +1 more location$190K - $285KRemoteLead and abovePythonC++CI/CD
- Principal ASIC Synthesis and Timing EngineerK2 Space · 🇺🇸United States - Remote$190K - $280KRemoteLead and aboveAnalog designASICRTL design
- Sr. Physical Design Flow & Methodology EngineerLightmatter · 🇺🇸Boston, MA$154K - $175KSeniorPythonLLMCI/CD
- Staff Engineer, Digital ASIC Design — Storage ControllersSK hynix memory solutions America Inc. · 🇺🇸San Jose—Lead and aboveMachine LearningVerilogStorage systems
- RTL Design Engineer, Networking / NoCOpenAI · 🇺🇸San Francisco$287K - $485KHybridVerilogHigh-performance computingASIC
- Physical Design and CAD EngineerAstera Labs · 🇺🇸San Jose, California, United States$160K - $200KPythonHardware interfacesCompilers
- DFT EngineerTenstorrent · 🇺🇸Austin, Texas, United States; Fort Collins, Colorado, Uni… · +1 more location—VerilogHardware interfacesCompilers
- Principal ASIC EngineerEchodyne Corp · 🇺🇸Kirkland, WA$165K - $247KLead and above
- Physical Design and Verification EngineerNeuralink · 🇺🇸South San Francisco, California, United States$131K - $265KPython
- Senior Microarchitecture ResearcherIonQ · 🇺🇸Bothell, Washington, United States; Boulder, Colorado, Un…$188K - $282KSeniorTechnical writingFinancial modelingRTL design
- Silicon Design LeadOpenAI · 🇺🇸San Francisco$287K - $485KHybridLead and aboveVerilogThreat modelingFirmware
- Principal PCS/PMA RTL Design EngineerAstera Labs · 🇺🇸San Jose, California, United States$185K - $240KLead and abovePythonVerilogPerl
- Staff Engineer, DFTAmbiq Micro, Inc. · 🇺🇸Austin, Texas, United States—Lead and above
- Hardware Engineers: RTL Implementation and Evaluation WorkflowsTerac · 🇺🇸United States—RemoteVerilogHardware testingASIC
- Principal SoC RTL EngineerAmbiq Micro, Inc. · 🇺🇸Austin, Texas, United States—Lead and aboveVerilog
- Director of Physical DesignAmbiq Micro, Inc. · 🇺🇸Austin, Texas, United States—Lead and above
- ASIC ArchitectDelos Data · 🇺🇸Palo Alto$160K - $280KHybridPythonC++Verilog
- STA/Timing Closure LeadAlpha Design Ai Inc · 🇺🇸San Jose—Lead and abovePython
- RTL LeadNormalComputing · 🇺🇸Mountain View$274K - $350KHybridLead and aboveVerilog
- Post-Silicon Validation Engineer, New GradSambaNova · 🇺🇸San Jose, California, United States$120K - $150KJuniorPythonC++Bash
- Physical Design Engineer, New GradSambaNova · 🇺🇸San Jose, California, United States$120K - $150KJuniorPythonPerlTest planning
- Sr. IC Package Design Engineer (Silicon Engineering)SpaceX · 🇺🇸Austin, TX · +1 more location—SeniorFirmwareAnalog designASIC
- Silicon Validation EngineerDensityAI · 🇺🇸Mountain View, CA$250K - $300KPythonC++Firmware
- Hardware Engineer, DFTNormalComputing · 🇺🇸Mountain View$232K - $304KHybridPython
- Senior Digital ASIC Design Engineer - DSP/Analog/SerDesCelero Communications, Inc. · 🇺🇸Irvine, CA · +1 more location$150K - $250KSeniorPythonMATLABVerilog
- Research Engineer, Chip Design RLAnthropic · 🇺🇸San Francisco, CA$500K - $850KLLMReinforcement learningASIC
- Post-Silicon Validation Engineer (Multiple Levels)Celero Communications, Inc. · 🇺🇸🇨🇦Irvine, CA, or Ottawa, Ontario, CanadaCA$100K - CA$200KPythonLoad testingFirmware
- Physical Design LeadNormalComputing · 🇺🇸Mountain View$200K - $400KHybridLead and abovePython
- Principal Post-Silicon Validation EngineerAstera Labs · 🇺🇸San Jose, California, United States$207K - $230KLead and abovePythonC++C
- RTL Design EngineerDelos Data · 🇺🇸Palo Alto$160K - $240KRemotePythonVerilog
- Microarchitect and RTL Designer - ComputeMatx · 🇺🇸Mountain View (HQ) or Remote$175K - $400KRemotePythonC++Verilog
- Staff ML Accelerator ArchitectWaymo · 🇺🇸Mountain View, CA, USA; New York, New York, USA$251K - $310KLead and aboveMachine LearningVerilogCompilers
- Post-Silicon Validation EngineerVoltai.careers · 🇺🇸Palo Alto Office—PythonC++
- Design for Test (DFT) EngineerVoltai.careers · 🇺🇸Palo Alto Office—Python
- Physical Design EngineerVoltai.careers · 🇺🇸Palo Alto Office—PythonMachine Learning
- RTL Design EngineerVoltai.careers · 🇺🇸Palo Alto Office—PythonVerilog
- Chip ArchitectVoltai.careers · 🇺🇸Palo Alto Office—PythonC++
- Applied Researcher - Chip DesignPrimeIntellect · 🇺🇸San Francisco—PythonLangChainDatadog
- Hardware Engineer, Physical DesignNormalComputing · 🇺🇸Mountain View$200K - $400KHybridPython
- ASIC ArchitectNormalComputing · 🇺🇸Mountain View$200K - $400KHybridPythonC++LLM
- Director ASIC Technical Program ManagementAstera Labs · 🇺🇸San Jose, California, United States$210K - $275KLead and aboveFirmwareHardware interfacesASIC
- DFT EngineerRicursive Intelligence · 🇺🇸Palo Alto—PythonVerilog
- Sr. ASIC Design Engineer (Silicon Engineering)SpaceX · 🇺🇸Palo Alto, CA · +3 more locations$175K - $280KSeniorPythonVerilogFirmware
- ASIC Design Engineer (Silicon Engineering)SpaceX · 🇺🇸Palo Alto, CA$135K - $175KPythonC++Bash
Showing the newest 50. See all 204 in search
Who is hiring for ASIC and chip design engineer roles in the United States
Where ASIC and chip design engineer roles in the United States are
- 🇺🇸United States204
- 🇺🇸California139
- 🇺🇸San Francisco Bay Area116
- 🇺🇸Texas42
- 🇺🇸Austin, TX41
- 🇺🇸Los Angeles, CA20
- 🇺🇸Seattle, WA17
- 🇨🇦Canada9
- 🇺🇸Boston, MA5
- 🇪🇺Europe4
A role that lists several places is counted in each of them.
What ASIC and chip design engineer roles in the United States pay, by level
| Level in the title | Median advertised salary | Roles counted |
|---|---|---|
| No level in the title | $218K | 50 |
| Senior | $210K | 35 |
| Lead and above | $235K | 45 |
Medians of the midpoints of advertised yearly US-dollar ranges; a level needs at least 15 such roles. Advertised, not verified pay.
Questions about ASIC and chip design engineer jobs in the United States
- How many ASIC and chip design engineer jobs in the United States are open right now?
- There are 204 open ASIC and chip design engineer jobs in the United States at 46 companies on Jobs Every Hour as of Nov 15, 2026. 11 of them were posted in the last seven days. The list is rebuilt every hour from the employers' own careers pages.
- Which companies have the most ASIC and chip design engineer jobs in the United States?
- Right now the most openings are at SpaceX (38), K2 Space (22), Tenstorrent (19), Astera Labs (11) and SambaNova (9). The ranking changes as companies open and close roles.
- Are there remote ASIC and chip design engineer jobs in the United States?
- 27 of the 204 open ASIC and chip design engineer jobs in the United States (13%) are listed as remote. Remote roles are often limited to certain countries or time zones, so check the location line of each job.
- What do ASIC and chip design engineer jobs in the United States pay?
- The median advertised salary is $218K, based on 134 open roles that publish a yearly US-dollar range. The middle half of those roles advertise between $210K and $245K. These are advertised ranges, not verified pay. Most employers here are technology companies, so the figures run above the wider market for the same work.
- Is it hard to get one of the ASIC and chip design engineer jobs in the United States?
- 5 of the 204 open ASIC and chip design engineer jobs in the United States (2%) are for beginners: junior roles and internships. Of the 140 postings that state experience, the median asks for 5 years. 46 companies are hiring and 11 roles were posted in the last seven days. Matching your resume to the skills each posting names helps most; the free resume builder shows the match.
- How is AI changing ASIC and chip design engineer jobs in the United States?
- 37 of the 204 open ASIC and chip design engineer jobs in the United States (18%) ask for AI or machine-learning skills, most often Machine Learning, LLM, AI. Employers still list 204 such roles today at 46 companies. Counted from the postings' own text on Nov 15, 2026.
- What skills do ASIC and chip design engineer jobs in the United States ask for?
- Most often Python (67%), ASIC (65%), RTL design (55%), Firmware (33%), Verilog (32%) of the 204 open postings, counted from their own text on Nov 15, 2026.
- Which job titles come up most in ASIC and chip design engineer jobs in the United States?
- Physical Design Engineer (17), RTL Design Engineer (5), Principal DFT Engineer (5), Staff Engineer (4), DFT Engineer (4): the most common titles among the 204 open roles, without the level and place notes in brackets.
- Are ASIC and chip design engineer jobs in the United States in demand in 2026?
- 204 ASIC and chip design engineer jobs in the United States are open on Jobs Every Hour today at 46 companies, 0.1% of all 148,162 open jobs here; 11 were posted in the last seven days. The median advertised salary is $218K. 27 (13%) can be done remotely.
- How do I apply for ASIC and chip design engineer jobs in the United States?
- Open a job and press “Apply on company site”. You go straight to the employer's own careers page and apply there. Jobs Every Hour needs no account and charges nothing for applying.