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ASIC and chip design engineer jobs in California
139 open roles for chip design engineers in California as of Nov 15, 2026. SpaceX, Tenstorrent, Astera Labs, SambaNova and Matx have the most. 12 are remote and the median advertised salary is $218K.
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Skills asked for in ASIC and chip design engineer roles in California
Bars show the share of these 139 roles; one role can count in several rows.
- Staff Engineer, Digital ASIC Design — Storage ControllersSK hynix memory solutions America Inc. · 🇺🇸San Jose—Lead and aboveMachine LearningVerilogStorage systems
- RTL Design Engineer, Networking / NoCOpenAI · 🇺🇸San Francisco$287K - $485KHybridVerilogHigh-performance computingASIC
- Physical Design and CAD EngineerAstera Labs · 🇺🇸San Jose, California, United States$160K - $200KPythonHardware interfacesCompilers
- DFT EngineerTenstorrent · 🇺🇸Austin, Texas, United States; Fort Collins, Colorado, Uni… · +1 more location—VerilogHardware interfacesCompilers
- Physical Design and Verification EngineerNeuralink · 🇺🇸South San Francisco, California, United States$131K - $265KPython
- Silicon Design LeadOpenAI · 🇺🇸San Francisco$287K - $485KHybridLead and aboveVerilogThreat modelingFirmware
- Principal PCS/PMA RTL Design EngineerAstera Labs · 🇺🇸San Jose, California, United States$185K - $240KLead and abovePythonVerilogPerl
- ASIC ArchitectDelos Data · 🇺🇸Palo Alto$160K - $280KHybridPythonC++Verilog
- STA/Timing Closure LeadAlpha Design Ai Inc · 🇺🇸San Jose—Lead and abovePython
- RTL LeadNormalComputing · 🇺🇸Mountain View$274K - $350KHybridLead and aboveVerilog
- Post-Silicon Validation Engineer, New GradSambaNova · 🇺🇸San Jose, California, United States$120K - $150KJuniorPythonC++Bash
- Physical Design Engineer, New GradSambaNova · 🇺🇸San Jose, California, United States$120K - $150KJuniorPythonPerlTest planning
- Sr. IC Package Design Engineer (Silicon Engineering)SpaceX · 🇺🇸Irvine, CA$165K - $265KSeniorFirmwareAnalog designASIC
- Silicon Validation EngineerDensityAI · 🇺🇸Mountain View, CA$250K - $300KPythonC++Firmware
- Hardware Engineer, DFTNormalComputing · 🇺🇸Mountain View$232K - $304KHybridPython
- Senior Digital ASIC Design Engineer - DSP/Analog/SerDesCelero Communications, Inc. · 🇺🇸Irvine, CA · +1 more location$150K - $250KSeniorPythonMATLABVerilog
- Research Engineer, Chip Design RLAnthropic · 🇺🇸San Francisco, CA$500K - $850KLLMReinforcement learningASIC
- Post-Silicon Validation Engineer (Multiple Levels)Celero Communications, Inc. · 🇺🇸🇨🇦Irvine, CA, or Ottawa, Ontario, CanadaCA$100K - CA$200KPythonLoad testingFirmware
- Physical Design LeadNormalComputing · 🇺🇸Mountain View$200K - $400KHybridLead and abovePython
- Principal Post-Silicon Validation EngineerAstera Labs · 🇺🇸San Jose, California, United States$207K - $230KLead and abovePythonC++C
- RTL Design EngineerDelos Data · 🇺🇸Palo Alto$160K - $240KRemotePythonVerilog
- Microarchitect and RTL Designer - ComputeMatx · 🇺🇸Mountain View (HQ) or Remote$175K - $400KRemotePythonC++Verilog
- Staff ML Accelerator ArchitectWaymo · 🇺🇸Mountain View, CA, USA; New York, New York, USA$251K - $310KLead and aboveMachine LearningVerilogCompilers
- Post-Silicon Validation EngineerVoltai.careers · 🇺🇸Palo Alto Office—PythonC++
- Design for Test (DFT) EngineerVoltai.careers · 🇺🇸Palo Alto Office—Python
- Physical Design EngineerVoltai.careers · 🇺🇸Palo Alto Office—PythonMachine Learning
- RTL Design EngineerVoltai.careers · 🇺🇸Palo Alto Office—PythonVerilog
- Chip ArchitectVoltai.careers · 🇺🇸Palo Alto Office—PythonC++
- Applied Researcher - Chip DesignPrimeIntellect · 🇺🇸San Francisco—PythonLangChainDatadog
- Hardware Engineer, Physical DesignNormalComputing · 🇺🇸Mountain View$200K - $400KHybridPython
- ASIC ArchitectNormalComputing · 🇺🇸Mountain View$200K - $400KHybridPythonC++LLM
- Director ASIC Technical Program ManagementAstera Labs · 🇺🇸San Jose, California, United States$210K - $275KLead and aboveFirmwareHardware interfacesASIC
- DFT EngineerRicursive Intelligence · 🇺🇸Palo Alto—PythonVerilog
- Sr. ASIC Design Engineer (Silicon Engineering)SpaceX · 🇺🇸Palo Alto, CA · +1 more location$175K - $280KSeniorPythonVerilogFirmware
- ASIC Design Engineer (Silicon Engineering)SpaceX · 🇺🇸Palo Alto, CA$135K - $175KPythonC++Bash
- Physical Design LeadPhinitylabs · 🇺🇸San Francisco—Lead and above
- Physical Design EngineerSK hynix memory solutions America Inc. · 🇺🇸San Jose—PythonMachine LearningPerl
- Senior ASIC RTL Design Engineer, AI HardwareCerebras · 🇺🇸Sunnyvale, CA$200K - $290KHybridSeniorPython.NETMachine Learning
- FPGA/ASIC Design Engineer (Silicon Engineering)SpaceX · 🇺🇸Irvine, CA$125K - $160KPythonC++Bash
- Post-Silicon Lab ManagerTenstorrent · 🇺🇸Santa Clara, California, United States—JiraConfluenceHardware interfaces
- Staff Engineer, Post-Silicon ValidationTenstorrent · 🇺🇸Austin, Texas, United States; Santa Clara, California, Un…—Lead and aboveLinuxFirmwareCompilers
- Sr. Staff / Principal Physical Design EngineerSK hynix memory solutions America Inc. · 🇺🇸San Jose—Lead and abovePythonMachine LearningPerl
- DFT EngineerDelos Data · 🇺🇸Palo Alto$160K - $260KRemotePythonVerilog
- SOC Integration EngineerMatx · 🇺🇸Mountain View$160K - $275KHybridPythonVerilogPerl
- Physical Design Engineer, TimingTenstorrent · 🇺🇸Austin, Texas, United States; Fort Collins, Colorado, Uni…—PythonPerlCompilers
- Senior Mixed-Signal Post-Silicon Validation EngineerK2 Space · 🇺🇸Los Angeles, CA$170K - $250KSeniorPythonFirmwareHardware testing
- Principal Physical Design EngineerCelero Communications, Inc. · 🇺🇸San Jose, CA · +1 more location$150K - $250KLead and abovePythonPerlAnalog design
- Senior RF/mmWave Post-Silicon Validation EngineerK2 Space · 🇺🇸Los Angeles, CA$170K - $250KSeniorPythonEthereumFirmware
- Senior Serdes Characterization & Post-Silicon Validation EngineerK2 Space · 🇺🇸Los Angeles, CA$170K - $250KSeniorPythonAmplitudeLoad testing
- Principal DFT EngineerCelero Communications, Inc. · 🇺🇸Irvine, California, United States$200K - $240KLead and abovePythonLinuxVerilog
Showing the newest 50. See all 139 in search
Who is hiring for ASIC and chip design engineer roles in California
Where ASIC and chip design engineer roles in California are
- 🇺🇸United States139
- 🇺🇸California139
- 🇺🇸San Francisco Bay Area116
- 🇺🇸Los Angeles, CA20
- 🇺🇸Austin, TX17
- 🇺🇸Texas17
- 🇨🇦Canada3
- 🇪🇺Europe1
- 🇪🇸Spain1
- 🇨🇦Toronto1
A role that lists several places is counted in each of them.
What ASIC and chip design engineer roles in California pay, by level
| Level in the title | Median advertised salary | Roles counted |
|---|---|---|
| No level in the title | $218K | 45 |
| Senior | $212K | 19 |
| Lead and above | $238K | 32 |
Medians of the midpoints of advertised yearly US-dollar ranges; a level needs at least 15 such roles. Advertised, not verified pay.
Questions about ASIC and chip design engineer jobs in California
- How many ASIC and chip design engineer jobs in California are open right now?
- There are 139 open ASIC and chip design engineer jobs in California at 30 companies on Jobs Every Hour as of Nov 15, 2026. 2 of them were posted in the last seven days. The list is rebuilt every hour from the employers' own careers pages.
- Which companies have the most ASIC and chip design engineer jobs in California?
- Right now the most openings are at SpaceX (22), Tenstorrent (16), Astera Labs (11), SambaNova (9) and Matx (9). The ranking changes as companies open and close roles.
- Are there remote ASIC and chip design engineer jobs in California?
- 12 of the 139 open ASIC and chip design engineer jobs in California (9%) are listed as remote. Remote roles are often limited to certain countries or time zones, so check the location line of each job.
- What do ASIC and chip design engineer jobs in California pay?
- The median advertised salary is $218K, based on 98 open roles that publish a yearly US-dollar range. The middle half of those roles advertise between $210K and $275K. These are advertised ranges, not verified pay. Most employers here are technology companies, so the figures run above the wider market for the same work.
- Is it hard to get one of the ASIC and chip design engineer jobs in California?
- 2 of the 139 open ASIC and chip design engineer jobs in California (1%) are for beginners: junior roles and internships. Of the 97 postings that state experience, the median asks for 6 years. 30 companies are hiring and 2 roles were posted in the last seven days. Matching your resume to the skills each posting names helps most; the free resume builder shows the match.
- How is AI changing ASIC and chip design engineer jobs in California?
- 28 of the 139 open ASIC and chip design engineer jobs in California (20%) ask for AI or machine-learning skills, most often Machine Learning, LLM, AI. Employers still list 139 such roles today at 30 companies. Counted from the postings' own text on Nov 15, 2026.
- What skills do ASIC and chip design engineer jobs in California ask for?
- Most often Python (72%), ASIC (64%), RTL design (58%), Verilog (35%), Firmware (30%) of the 139 open postings, counted from their own text on Nov 15, 2026.
- Which job titles come up most in ASIC and chip design engineer jobs in California?
- Physical Design Engineer (14), RTL Design Engineer (5), DFT Engineer (4), Post (4), Principal Physical Design Engineer (4): the most common titles among the 139 open roles, without the level and place notes in brackets.
- Are ASIC and chip design engineer jobs in California in demand in 2026?
- 139 ASIC and chip design engineer jobs in California are open on Jobs Every Hour today at 30 companies, 0.1% of all 148,162 open jobs here; 2 were posted in the last seven days. The median advertised salary is $218K. 12 (9%) can be done remotely.
- How do I apply for ASIC and chip design engineer jobs in California?
- Open a job and press “Apply on company site”. You go straight to the employer's own careers page and apply there. Jobs Every Hour needs no account and charges nothing for applying.