Principal DFT Engineer is open at Celero Communications, Inc. in Irvine, California, United States. The posting gives a salary of $200K - $240K. Posted on Sep 16, 2026, and still on Celero Communications, Inc.’s careers page when we last checked, on Nov 14, 2026.
About the role
Develop and implement DFT architecture for ASIC and SoC designs. Perform scan insertion, scan chain planning, and scan compression implementation. Generate and validate ATPG patterns and analyze fault coverage results. Implement and verify MBIST, and other on-chip test features. Collaborate with RTL, verification, and physical design teams to ensure successful DFT integration. Support JTAG and boundary-scan…
The opening lines of the posting. The rest is on Celero Communications, Inc.’s careers page.
Hiring at Celero Communications, Inc.
Celero Communications, Inc. has 26 open roles right now. Most are in Engineering, Marketing & Community and Operations. The median advertised salary across its roles with a published range is $200K. See all its roles
