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RTL Design Engineer

Delos Data · Palo Alto
Remote$160K - $240KEquityPythonVerilog

RTL Design Engineer is open at Delos Data in Palo Alto (remote). The posting gives a salary of $160K - $240K. Posted on Oct 20, 2026, and still on Delos Data’s careers page when we last checked, on Nov 14, 2026.

About the role

· Design and implement RTL for complex digital subsystems using Verilog/SystemVerilog · Translate architectural specifications into clean, efficient, and scalable microarchitectures · Collaborate with architecture, verification, and physical design teams to ensure design correctness and closure · Develop high-quality, reusable RTL with strong coding standards and documentation · Perform linting, CDC analysis, and…

The opening lines of the posting. The rest is on Delos Data’s careers page.

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