Senior Physical Design Engineer (Synthesis, SDC & STA)

Every constraint you write decides whether a chip closes timing or slips a tapeout. You'll own the front end of the physical design flow on advanced nodes, turning RTL into clean netlists with constraints that hold from synthesis all the way to signoff. When the timing report looks wrong, you're the one who knows whether it's the design, the constraint, or the tool. WHAT YOU'LL DO Own synthesis for complex blocks…

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