Senior Digital ASIC Design Engineer - DSP/Analog/SerDes is open at Celero Communications, Inc. in Ottawa, Ontario, Canada. Posted on Oct 21, 2026, and still on Celero Communications, Inc.’s careers page when we last checked, on Nov 14, 2026.
About the role
Design and implement high-performance digital circuits and ASIC blocks using Verilog and SystemVerilog. • Develop and integrate DSP, digital communication, and high-speed SerDes functionality into complex ASIC designs. • Work closely with Analog, SerDes, DSP, Architecture, Verification, Physical Design, and Systems teams to develop and integrate mixed-signal ASICs. • Participate in the design and development of…
The opening lines of the posting. The rest is on Celero Communications, Inc.’s careers page.
Hiring at Celero Communications, Inc.
Celero Communications, Inc. has 26 open roles right now. Most are in Engineering, Marketing & Community and Operations. The median advertised salary across its roles with a published range is $200K. See all its roles
