What is the average ASIC and Chip Design Engineer salary?

$230K a year on average and $218K at the median, across 136 open ASIC and Chip Design Engineer postings at companies that state pay (November 2026). The median is the better guide: a few very high offers pull the average up.

What is the typical range?

The middle half of the postings offer $210K to $245K a year. A quarter offer less and a quarter offer more.

Which companies advertise the highest ASIC and Chip Design Engineer pay?

OpenAI ($376K), NormalComputing ($300K), Waymo ($280K), by the median of their open postings that state pay (three postings or more).

Is an asic and chip design engineer a high-paying job?

The median ASIC and Chip Design Engineer posting advertises $218K a year, more than the median of all 55,899 job postings with pay on Jobs Every Hour ($174K). That is 25% above the middle of the market.

How much can you earn as an asic and chip design engineer?

A tenth of the postings offer $300K a year or more; the highest open ASIC and Chip Design Engineer role advertises up to $850K. Pay rises with level: see the table by level.

What is the ASIC and Chip Design Engineer salary per hour and per month?

The median of $218K a year is about $105 an hour (2,080 working hours) and $18,125 a month before tax. The middle half of postings: $101 to $118 an hour.

Which skills pay more for ASIC and Chip Design Engineer roles?

Postings that ask for Compilers (+$32K, 16 postings), Cadence (+$14K, 24 postings), RTL design (+$2K, 77 postings) advertise more than the $218K median of all ASIC and Chip Design Engineer postings with pay.

Where do these figures come from?

From the pay ranges employers print in their own job postings, read from their careers pages every hour. The midpoint of each range is counted. These are advertised ranges for open roles, mostly in the United States and in US dollars, not what people are actually paid.

ASIC and Chip Design Engineer Salary: $230K Average, $218K Median

ASIC and Chip Design Engineer salary by level

Lead roles advertise a median of $235K, 12% more than senior roles ($210K). The level comes from the job title; titles without a level word are counted separately.

Level	Median salary	Middle half	Roles
Senior	$210K	$210K–$220K	35
Lead and above	$235K	$218K–$250K	45
No level in the title	$218K	$180K–$300K	52

ASIC and Chip Design Engineer salary by location

Name	Median salary	Roles counted
🇺🇸San Francisco Bay Area	$228K	80
🇺🇸California	$218K	98
🇺🇸United States	$218K	134
🇺🇸Los Angeles, CA	$211K	18
🇺🇸Seattle, WA	$210K	17

Skills that pay more for ASIC and Chip Design Engineer roles

Skill	Median with it	Above the median	Postings
Compilers	$250K	+$32K	16
Cadence	$231K	+$14K	24
RTL design	$220K	+$2K	77

Top-paying companies

Name	Median salary	Roles counted
OpenAI	$376K	6
NormalComputing	$300K	6
Waymo	$280K	3
DensityAI	$270K	3
Samsung Research America	$251K	4
Cerebras	$245K	3
Lightmatter	$242K	5
SambaNova	$218K	9
Matx	$218K	9
SpaceX	$212K	28
Astera Labs	$212K	11
Delos Data	$210K	4
K2 Space	$210K	22
Celero Communications, Inc.	$200K	5

Highest-paying open ASIC and Chip Design Engineer roles

All ASIC and chip design engineer jobs

Research Engineer, Chip Design RLAnthropic · 🇺🇸San Francisco, CA$500K - $850KLLMReinforcement learningASIC3w
Research Engineer, AI for Chip DesignOpenAI · 🇺🇸San Francisco$380K - $500KHybridAIVerilogLLM evaluation2mo
Silicon EngineerAnthropic · 🇺🇸San Francisco, CA$320K - $485KMachine LearningAnalog designCompilers3mo
Physical Design EngineerOpenAI · 🇺🇸San Francisco$225K - $485KPythonBazelHigh-performance computing2mo
Physical Design Engineer, HardwareRiver AI Inc. · 🇺🇸Palo Alto, CA; Austin, TX$200K - $420KPythonDeep learningSlack6mo
RTL Design Engineer, HardwareRiver AI Inc. · 🇺🇸Palo Alto, CA$200K - $420KPythonC++Verilog6mo
ASIC ArchitectNormalComputing · 🇺🇸Mountain View$200K - $400KHybridPythonC++LLM4w
Hardware Engineer, RTLNormalComputing · 🇺🇸Mountain View$200K - $400KHybridVerilog3mo
Microarchitect and RTL Designer - ComputeMatx · 🇺🇸Mountain View (HQ) or Remote$175K - $400KRemotePythonC++Verilog3w
Principal Engineer, SoC NPU ArchitectSamsung Research America · 🇺🇸665 Clyde Avenue, Mountain View, CA, USA$242K - $377KLead and abovePythonC++Machine Learning2mo
Principal DFT Engineer (Silicon Engineering)SpaceX · 🇺🇸Palo Alto, CA$220K - $355KLead and abovePythonVerilogPerl3mo
ASIC Network ArchitectSambaNova · 🇺🇸Austin, Texas, United States; Remote - US; San Jose, Cali…$250K - $350KRemoteRustPythonC++4mo
Director of ASIC Design VerificationSambaNova · 🇺🇸San Jose, California, United States$270K - $340KLead and abovePythonMachine LearningVerilog2mo
Principal DFT Engineer (Silicon Engineering)SpaceX · 🇺🇸Irvine, CA$210K - $340KLead and abovePythonVerilogPerl3mo
Physical Design Timing EngineerDensityAI · 🇺🇸Mountain View, CA$220K - $320KCompilersRTL designCadence5mo
Staff ML Accelerator ArchitectWaymo · 🇺🇸Mountain View, CA, USA; New York, New York, USA$251K - $310KLead and aboveMachine LearningVerilogCompilers3w
Staff SoC Design EngineerWaymo · 🇺🇸Mountain View, CA, USA$251K - $310KLead and abovePythonC++Scala3mo
3D Stacked DRAM - Logic Design EngineerSK hynix America · 🇺🇸San Jose, CA$140K - $310KVerilog4mo
HBM Architect - Logic DesignSK hynix America · 🇺🇸San Jose, CA$140K - $310K3mo
Senior Staff Engineer, SoC NPU ArchitectSamsung Research America · 🇺🇸665 Clyde Avenue, Mountain View, CA, USA$204K - $306KLead and abovePythonC++Machine Learning2mo

Questions about ASIC and Chip Design Engineer pay

What is the average ASIC and Chip Design Engineer salary?: $230K a year on average and $218K at the median, across 136 open ASIC and Chip Design Engineer postings at companies that state pay (November 2026). The median is the better guide: a few very high offers pull the average up.
What is the typical range?: The middle half of the postings offer $210K to $245K a year. A quarter offer less and a quarter offer more.
Which companies advertise the highest ASIC and Chip Design Engineer pay?: OpenAI ($376K), NormalComputing ($300K), Waymo ($280K), by the median of their open postings that state pay (three postings or more).
Is an asic and chip design engineer a high-paying job?: The median ASIC and Chip Design Engineer posting advertises $218K a year, more than the median of all 55,899 job postings with pay on Jobs Every Hour ($174K). That is 25% above the middle of the market.
How much can you earn as an asic and chip design engineer?: A tenth of the postings offer $300K a year or more; the highest open ASIC and Chip Design Engineer role advertises up to $850K. Pay rises with level: see the table by level.
What is the ASIC and Chip Design Engineer salary per hour and per month?: The median of $218K a year is about $105 an hour (2,080 working hours) and $18,125 a month before tax. The middle half of postings: $101 to $118 an hour.
Which skills pay more for ASIC and Chip Design Engineer roles?: Postings that ask for Compilers (+$32K, 16 postings), Cadence (+$14K, 24 postings), RTL design (+$2K, 77 postings) advertise more than the $218K median of all ASIC and Chip Design Engineer postings with pay.
Where do these figures come from?: From the pay ranges employers print in their own job postings, read from their careers pages every hour. The midpoint of each range is counted. These are advertised ranges for open roles, mostly in the United States and in US dollars, not what people are actually paid.

ASIC and Chip Design Engineer salary: $218K median