https://jobseveryhour.com/skills/rtl-design/RTL design jobs — Jobs Every HourSun, 15 Nov 2026 19:27:33 +0000https://jobseveryhour.com/job/senior-fpga-verification-engineer-anduril-industries-3/https://jobseveryhour.com/job/senior-fpga-verification-engineer-anduril-industries-3/Fri, 13 Nov 2026 00:00:00 +0000Waltham, Massachusetts, United States. The Imaging team is seeking a Senior FPGA Verification Engineer to help design a new product lines. In this role, you will work closely with an interdisciplinary technical team to define, complete the design and analysis, build prototypes leading to ground and flight testing, and mature the prototypes into products. WHAT YOU’LL DO Verification environment architecture and design using tools like SystemVerilog or…https://jobseveryhour.com/job/senior-fpga-verification-engineer-anduril-industries/https://jobseveryhour.com/job/senior-fpga-verification-engineer-anduril-industries/Fri, 13 Nov 2026 00:00:00 +0000Goleta, California, United States. The Imaging team is seeking a Senior FPGA Verification Engineer to help design a new product lines. In this role, you will work closely with an interdisciplinary technical team to define, complete the design and analysis, build prototypes leading to ground and flight testing, and mature the prototypes into products. WHAT YOU’LL DO Verification environment architecture and design using tools like SystemVerilog or…https://jobseveryhour.com/job/senior-fpga-verification-engineer-anduril-industries-2/https://jobseveryhour.com/job/senior-fpga-verification-engineer-anduril-industries-2/Fri, 13 Nov 2026 00:00:00 +0000Boulder, Colorado, United States. The Imaging team is seeking a Senior FPGA Verification Engineer to help design a new product lines. In this role, you will work closely with an interdisciplinary technical team to define, complete the design and analysis, build prototypes leading to ground and flight testing, and mature the prototypes into products. WHAT YOU’LL DO Verification environment architecture and design using tools like SystemVerilog or…https://jobseveryhour.com/job/senior-firmware-engineer-anduril-industries/https://jobseveryhour.com/job/senior-firmware-engineer-anduril-industries/Fri, 13 Nov 2026 00:00:00 +0000Waltham, Massachusetts, United States. The Imaging team is seeking a Senior Firmware Engineer to design a new product lines. In this role, you will work closely with an interdisciplinary technical team to define, complete the design and analysis, build prototypes leading to ground and flight testing, and mature the prototypes into products. WHAT YOU’LL DO Lead FPGA architecture, standards, development and review processes FPGA Development : Designing…https://jobseveryhour.com/job/senior-embedded-engineer-anduril-industries/https://jobseveryhour.com/job/senior-embedded-engineer-anduril-industries/Fri, 13 Nov 2026 00:00:00 +0000Waltham, Massachusetts, United States. The Imaging team is seeking a Senior Embedded Engineer to design a new product lines. In this role, you will work closely with an interdisciplinary technical team to define, complete the design and analysis, build prototypes leading to ground and flight testing, and mature the prototypes into products. WHAT YOU’LL DO Lead FPGA architecture, standards, development and review processes FPGA Development : Designing…https://jobseveryhour.com/job/senior-fpga-prototyping-engineer-k2-space-2/https://jobseveryhour.com/job/senior-fpga-prototyping-engineer-k2-space-2/Wed, 11 Nov 2026 00:00:00 +0000United States - Remote. We are seeking a Senior FPGA & Silicon Bring-up Engineer to accelerate the development of next-generation communications ASICs. You will own FPGA prototyping, firmware enablement, first-silicon bring-up, and hardware validation, serving as the bridge between ASIC design, firmware, software, and system integration. This role spans the entire silicon lifecycle from pre-silicon FPGA platforms that enable early…https://jobseveryhour.com/job/senior-asic-physical-design-engineer-k2-space-2/https://jobseveryhour.com/job/senior-asic-physical-design-engineer-k2-space-2/Wed, 11 Nov 2026 00:00:00 +0000United States - Remote. We are seeking a Senior ASIC Physical Design Engineer to help implement advanced SoCs that power next-generation satellite and space systems. In this role, you will contribute to the full physical design flow—from synthesis to GDSII—working closely with architecture, RTL, verification, and packaging teams. You’ll be a key contributor in achieving timing closure, optimizing PPA, and supporting design integration with…https://jobseveryhour.com/job/senior-asic-design-verification-engineer-k2-space/https://jobseveryhour.com/job/senior-asic-design-verification-engineer-k2-space/Wed, 11 Nov 2026 00:00:00 +0000United States - Remote. We are seeking a Senior ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ownership, deep technical…https://jobseveryhour.com/job/principal-asic-physical-design-engineer-k2-space-2/https://jobseveryhour.com/job/principal-asic-physical-design-engineer-k2-space-2/Wed, 11 Nov 2026 00:00:00 +0000United States - Remote. We are looking for a Principal ASIC Physical Design Engineer to lead the implementation of complex SoCs for next-generation satellite and space systems. You will own the full physical design flow—from RTL handoff to GDSII—and collaborate closely with architecture, RTL design, DFT, and packaging teams. This role also involves managing external physical design partners, driving tool and flow decisions, and ensuring…https://jobseveryhour.com/job/principal-asic-design-verification-engineer-k2-space/https://jobseveryhour.com/job/principal-asic-design-verification-engineer-k2-space/Wed, 11 Nov 2026 00:00:00 +0000United States - Remote. We are seeking a Principal ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ownership, deep technical…https://jobseveryhour.com/job/principal-asic-synthesis-and-timing-engineer-k2-space/https://jobseveryhour.com/job/principal-asic-synthesis-and-timing-engineer-k2-space/Wed, 11 Nov 2026 00:00:00 +0000United States - Remote. We are looking for a Principal ASIC Synthesis and Timing Engineer to lead the implementation of complex SoCs for next-generation satellite and space systems. You will own the constraints development and validation—from RTL handoff to synthesis —and collaborate closely with architecture, RTL design, DFT, and physical design team. This role also involves managing external physical design partners, driving convergence…https://jobseveryhour.com/job/sr-physical-design-flow-methodology-engineer-lightmatter/https://jobseveryhour.com/job/sr-physical-design-flow-methodology-engineer-lightmatter/Wed, 11 Nov 2026 00:00:00 +0000Boston, MA. Develop, maintain and extend our physical design flows from synthesis through signoff (place-and-route, CTS, STA, power integrity, DRC/LVS), mostly in Python and TCL. Use AI and LLM-based tools to automate flow tasks such as report triage, debug, constraint checking, DRC/LVS analysis, run monitoring and QoR prediction. Research and prototype new flow capabilities, EDA tool features and methodologies, then turn the…https://jobseveryhour.com/job/senior-hardware-design-engineer-arago/https://jobseveryhour.com/job/senior-hardware-design-engineer-arago/Wed, 11 Nov 2026 00:00:00 +0000Paris Offices. Design and verify custom digital hardware components and architectures that enable high-performance, tightly integrated computation workloads and interface Arago’s custom tensor unit for advanced AI/ML applications. RESPONSIBILITIES - Design, implement, and verify RTL blocks for memory, control, and compute subsystems within Arago’s custom multiphysics computation unit. - Collaborate with Arago’s system software and…https://jobseveryhour.com/job/staff-engineer-digital-asic-design-storage-controllers-sk-hynix-memory-solutions-america-inc/https://jobseveryhour.com/job/staff-engineer-digital-asic-design-storage-controllers-sk-hynix-memory-solutions-america-inc/Tue, 10 Nov 2026 00:00:00 +0000San Jose. Join our digital ASIC design team to develop IP for next-generation SSD controllers and storage solutions. This role offers opportunities across the controller architecture, including host interfaces, on-chip interconnects, and back-end NAND subsystems. You will translate product requirements into microarchitecture specifications, implement high-quality RTL, and collaborate with verification and physical design…https://jobseveryhour.com/job/rtl-design-engineer-networking-noc-openai/https://jobseveryhour.com/job/rtl-design-engineer-networking-noc-openai/Tue, 10 Nov 2026 00:00:00 +0000San Francisco. We’re looking for an RTL Design Engineer to help design and develop next-generation AI accelerator silicon. In this role, you'll work across architecture, microarchitecture, and RTL implementation, translating complex system and performance requirements into efficient, scalable hardware designs. You'll collaborate closely with silicon architects, hardware and software engineers, verification, and physical design…https://jobseveryhour.com/job/engineer-cpu-performance-verification-tenstorrent/https://jobseveryhour.com/job/engineer-cpu-performance-verification-tenstorrent/Sun, 08 Nov 2026 00:00:00 +0000Austin, Texas, United States; Santa Clara, California, United States. Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for…https://jobseveryhour.com/job/principal-design-verification-engineer-ai-fabric-switches-astera-labs/https://jobseveryhour.com/job/principal-design-verification-engineer-ai-fabric-switches-astera-labs/Sat, 07 Nov 2026 00:00:00 +0000San Jose, California, United States. Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software…https://jobseveryhour.com/job/sr-staff-digital-design-engineer-lightmatter-3/https://jobseveryhour.com/job/sr-staff-digital-design-engineer-lightmatter-3/Fri, 06 Nov 2026 00:00:00 +0000Toronto, ON. Develop RTL (i.e. system Verilog) modules with DFT considerations for IC development Debug complex logic and mixed signal simulations Understand and integrate silicon photonic communication and compute technology into digital accelerator design Actively work with Architecture, Design Verification, Physical Design, Photonic, Analog and Software teams to realize high performance, low power designs in advanced…https://jobseveryhour.com/job/sr-staff-digital-design-engineer-lightmatter-2/https://jobseveryhour.com/job/sr-staff-digital-design-engineer-lightmatter-2/Fri, 06 Nov 2026 00:00:00 +0000Boston, MA. Develop RTL (i.e. system Verilog) modules with DFT considerations for IC development Debug complex logic and mixed signal simulations Understand and integrate silicon photonic communication and compute technology into digital accelerator design Actively work with Architecture, Design Verification, Physical Design, Photonic, Analog and Software teams to realize high performance, low power designs in advanced…https://jobseveryhour.com/job/sr-staff-digital-design-engineer-lightmatter/https://jobseveryhour.com/job/sr-staff-digital-design-engineer-lightmatter/Fri, 06 Nov 2026 00:00:00 +0000Mountain View, CA. Develop RTL (i.e. system Verilog) modules with DFT considerations for IC development Debug complex logic and mixed signal simulations Understand and integrate silicon photonic communication and compute technology into digital accelerator design Actively work with Architecture, Design Verification, Physical Design, Photonic, Analog and Software teams to realize high performance, low power designs in advanced…https://jobseveryhour.com/job/physical-design-and-cad-engineer-astera-labs/https://jobseveryhour.com/job/physical-design-and-cad-engineer-astera-labs/Fri, 06 Nov 2026 00:00:00 +0000San Jose, California, United States. As a Physical Design & CAD Engineer , you will serve as a Technical Lead developing Astera Labs’ next-generation connectivity ASICs for cloud and AI infrastructure. This role combines Physical Design CAD methodology development with hands-on place-and-route (PNR) implementation. You will develop and optimize automated design flows for advanced process nodes while contributing to block-level physical design, timing…https://jobseveryhour.com/job/dft-engineer-tenstorrent-2/https://jobseveryhour.com/job/dft-engineer-tenstorrent-2/Fri, 06 Nov 2026 00:00:00 +0000Austin, Texas, United States; Fort Collins, Colorado, United States; Santa Clara, California, United States. is Design for Test (DFT) for high-performance designs going into industry leading AI/ML architectures. The person coming into this role will be involved in all implementation aspects from RTL to tapeout for various IPs on the chip. High level challenges include reducing test cost while attaining high coverage, and facilitating debug and yield learnings while minimizing design intrusions. The work is done…https://jobseveryhour.com/job/fpga-engineer-tomorrow-io/https://jobseveryhour.com/job/fpga-engineer-tomorrow-io/Fri, 06 Nov 2026 00:00:00 +0000Golden, Colorado, United States. , you will translate high level design requirements into concrete digital logic designs and contribute to the development of our custom electronic hardware. You will join a collaborative, high-performing environment that values technical excellence, shared accountability, and the pursuit of ambitious, mission-driven engineering goals. PLEASE NOTE: This position requires access to technology that is controlled under…https://jobseveryhour.com/job/principal-design-engineer-astera-labs/https://jobseveryhour.com/job/principal-design-engineer-astera-labs/Fri, 06 Nov 2026 00:00:00 +0000San Jose, California, United States. We are looking for Principal Design Engineers with experience developing micro-architecture and implementation of the front-end circuit design, including RTL, synthesis, IP integration, and block-level verification for high performance network controllers. The candidate must have good knowledge of communication/interface protocols such as PCI-Express (Gen-3 and above), Ualink, Esun, Ethernet etc. Basic…https://jobseveryhour.com/job/senior-microarchitecture-researcher-ionq/https://jobseveryhour.com/job/senior-microarchitecture-researcher-ionq/Thu, 05 Nov 2026 00:00:00 +0000Bothell, Washington, United States; Boulder, Colorado, United States; College Park, Maryland, United States. Role: We are looking for a Microarchitecture (uArch) Researcher. As a uArch researcher, you will be part of a cross-functional team whose mission is to lead IonQ on its journey to build the world's best quantum computers to solve the world's most complex problems. In this role, you will contribute to the physical implementation, design and layout of fault-tolerant architectures in ion trap quantum processors. You…https://jobseveryhour.com/job/principal-formal-verification-engineer-astera-labs/https://jobseveryhour.com/job/principal-formal-verification-engineer-astera-labs/Thu, 05 Nov 2026 00:00:00 +0000Bengaluru, Karnataka, India. We are looking for a Principal Formal Verification Engineer with 10+ years of experience to lead formal verification efforts for complex semiconductor and silicon designs. This role will be responsible for driving verification strategy, improving design quality, and mentoring engineers while working closely with design, architecture, and validation teams. Key Responsibilities Lead formal verification activities for…https://jobseveryhour.com/job/manager-capital-markets-figure-lending/https://jobseveryhour.com/job/manager-capital-markets-figure-lending/Thu, 05 Nov 2026 00:00:00 +0000Remote; Reno, NV; Charlotte, NC. We’re looking for a Manager, Capital Markets to join our growing team! As Manager within the Capital Markets team, you’ll own day-to-day execution of our secondary transactions, including whole loan trades, liquidity, and warehouse sales and repurchases, while supporting securitizations and investor initiatives. You’ll help scale the settlement, pipeline, and reporting processes behind Figure’s growing origination…https://jobseveryhour.com/job/silicon-design-lead-openai/https://jobseveryhour.com/job/silicon-design-lead-openai/Wed, 04 Nov 2026 00:00:00 +0000San Francisco. We’re looking for a Silicon Design Lead to drive architecture, microarchitecture, and implementation of key IP and subsystems for our AI hardware platforms. You will translate functional, performance, and security requirements into efficient silicon designs, owning technical decisions from architectural definition through implementation and integration. Part of this role will focus on hardware security…https://jobseveryhour.com/job/mixed-signal-ic-design-engineer-arago/https://jobseveryhour.com/job/mixed-signal-ic-design-engineer-arago/Wed, 04 Nov 2026 00:00:00 +0000Paris Offices. Design, integrate, and deliver high-performance digital subsystems within mixed-signal ICs, enabling control, calibration, and high-speed data movement in analog-centric environments — owning the flow from RTL to physical implementation and tape-out. RESPONSIBILITIES - Design and verify digital subsystems that interface directly with high-speed analog and mixed-signal circuits — including calibration engines…https://jobseveryhour.com/job/staff-cloud-hypervisor-engineer-compute-crusoe/https://jobseveryhour.com/job/staff-cloud-hypervisor-engineer-compute-crusoe/Tue, 03 Nov 2026 00:00:00 +0000Sunnyvale, CA - US. At Crusoe, we are building the "engine room" of the AI revolution. We are seeking a Staff Cloud Hypervisor R&D Engineer to serve as the lead architect for our next-generation virtualization stack. In this role, you will move beyond standard virtualization to design a "Greenfield" hypervisor environment where GPUs, DPUs, and high-speed interconnects are first-class citizens. You will be responsible for eliminating…https://jobseveryhour.com/job/principal-pcs-pma-rtl-design-engineer-astera-labs/https://jobseveryhour.com/job/principal-pcs-pma-rtl-design-engineer-astera-labs/Tue, 03 Nov 2026 00:00:00 +0000San Jose, California, United States. PCS/PMA RTL design and implementation Develop synthesizable Verilog/SystemVerilog RTL for PCS and PMA digital blocks supporting Ethernet, PCIe, UCIe, UALink, and related protocols. Implement PCS functions such as line encoding/decoding (64b/66b, 128b/130b, 8b/10b), scrambling/descrambling, block and word alignment, lane deskew and reordering, gearboxes, elastic buffers/FIFOs, and rate adaptation. Implement forward…https://jobseveryhour.com/job/eda-cloud-developer-infrastructure-engineer-openai/https://jobseveryhour.com/job/eda-cloud-developer-infrastructure-engineer-openai/Tue, 03 Nov 2026 00:00:00 +0000San Francisco. We’re looking for an Infrastructure Software Engineer to build and scale the infrastructure and developer workflows that power OpenAI’s custom silicon development. You’ll work closely with engineering teams across design verification, physical design, emulation, formal verification, and systems software to develop reliable, automated, and efficient workflows that accelerate hardware development. In this role, you'll…https://jobseveryhour.com/job/technical-lead-digital-design-engineer-astera-labs/https://jobseveryhour.com/job/technical-lead-digital-design-engineer-astera-labs/Mon, 02 Nov 2026 00:00:00 +0000San Jose, California, United States. Own the RTL implementation of complex digital designs from micro-architecture through sign-off. Collaborate with verification teams to review test plans and debug issues. Support efforts to achieve timing closure and implement Design-for-Test (DFT) features. Scripting and automation for ASIC methodology improvement. Accountable for quality and overall design success with the support of senior engineers. Required…https://jobseveryhour.com/job/sr-software-engineer-systems-framework-infrastructure-tenstorrent/https://jobseveryhour.com/job/sr-software-engineer-systems-framework-infrastructure-tenstorrent/Mon, 02 Nov 2026 00:00:00 +0000Toronto, Ontario, Canada. , you will focus on developing software frameworks, APIs, tooling, infrastructure, and continuous integration (CI) regression systems to introspect and test our ASICs and systems, while supporting teams across Tenstorrent. You will gain experience with state-of-the-art ML processor architecture, board design, and debugging. This role is hybrid, based out of Toronto, Canada. We welcome candidates at various…https://jobseveryhour.com/job/principal-physical-design-cad-engineer-astera-labs/https://jobseveryhour.com/job/principal-physical-design-cad-engineer-astera-labs/Sun, 01 Nov 2026 00:00:00 +0000Tel Aviv-Yafo, Tel Aviv District, Israel. Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, We are looking for a Physical Design CAD Engineer with at least 3 years of hands-on experience in digital implementation flows. The ideal candidate is highly technical, curious, and…https://jobseveryhour.com/job/staff-principal-physical-design-sta-engineer-astera-labs-2/https://jobseveryhour.com/job/staff-principal-physical-design-sta-engineer-astera-labs-2/Sun, 01 Nov 2026 00:00:00 +0000Haifa District, Israel. Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Static Timing Analysis (STA) Engineer to join our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful…https://jobseveryhour.com/job/staff-principal-asic-design-engineer-astera-labs/https://jobseveryhour.com/job/staff-principal-asic-design-engineer-astera-labs/Sun, 01 Nov 2026 00:00:00 +0000Haifa District, Israel. Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Staff / Principal ASIC Design Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful…https://jobseveryhour.com/job/dft-engineer-astera-labs/https://jobseveryhour.com/job/dft-engineer-astera-labs/Sun, 01 Nov 2026 00:00:00 +0000Haifa District, Israel. Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary DFT Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new…https://jobseveryhour.com/job/staff-dft-engineer-astera-labs/https://jobseveryhour.com/job/staff-dft-engineer-astera-labs/Sun, 01 Nov 2026 00:00:00 +0000Haifa District, Israel. Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Staff DFT Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a…https://jobseveryhour.com/job/principal-dft-engineer-astera-labs-3/https://jobseveryhour.com/job/principal-dft-engineer-astera-labs-3/Sun, 01 Nov 2026 00:00:00 +0000Haifa District, Israel. Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Principal DFT Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership…https://jobseveryhour.com/job/physical-design-team-lead-astera-labs-2/https://jobseveryhour.com/job/physical-design-team-lead-astera-labs-2/Sun, 01 Nov 2026 00:00:00 +0000Haifa District, Israel. Astera Labs is a hyper-growth connectivity company building the purpose-built silicon that powers rack-scale AI infrastructure. As a Principal Physical Design Engineer and Team Lead in Israel, you will lead physical design teams that take complex, high-speed mixed-signal and digital SoCs from RTL handoff through tapeout. You will set the technical direction, drive execution across multiple projects, and grow the…https://jobseveryhour.com/job/senior-asic-design-engineer-astera-labs/https://jobseveryhour.com/job/senior-asic-design-engineer-astera-labs/Sun, 01 Nov 2026 00:00:00 +0000Haifa District, Israel. Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Senior ASIC Design Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful product…https://jobseveryhour.com/job/hardware-engineers-rtl-implementation-and-evaluation-workflo-terac/https://jobseveryhour.com/job/hardware-engineers-rtl-implementation-and-evaluation-workflo-terac/Sat, 31 Oct 2026 00:00:00 +0000United States. Walk us through your approach to RTL implementation and hardware description - Review and react to specific automated evaluation scenarios - Describe a recent time you tackled a complex hardware verification challenge - Provide feedback on current workflows and tooling gaps WHO SHOULD APPLY - Professional experience in hardware engineering or RTL design - Hands-on background with hardware description languages…https://jobseveryhour.com/job/fpga-engineer-anduril-industries/https://jobseveryhour.com/job/fpga-engineer-anduril-industries/Sat, 31 Oct 2026 00:00:00 +0000Broomfield, Colorado, United States; Fort Collins, Colorado, United States. , you will work closely with an interdisciplinary technical team to define FPGA designs, determine solutions, build prototypes, perform testing, and mature the prototypes into products. About the Job We are looking for an FPGA Engineer to join our growing team in Fort Collins, CO. You will develop and verify FPGA designs that control radar hardware, move high-rate sensor data, and support real-time signal…https://jobseveryhour.com/job/electrical-engineer-sdr-hardware-astranis/https://jobseveryhour.com/job/electrical-engineer-sdr-hardware-astranis/Fri, 30 Oct 2026 00:00:00 +0000San Francisco. for you! You will work closely with the RTL, Comms, and RF designs to help design the best possible radio systems for our payload and TTC systems. Role Design and test ultra high speed digital data systems Work with state of the art FPGAs and data converters Design and lay out PCBs to implement these systems Test and validate full radio signal chain Integrate these systems into the spacecraft by working closely with…https://jobseveryhour.com/job/dsp-integration-test-engineer-attotude/https://jobseveryhour.com/job/dsp-integration-test-engineer-attotude/Fri, 30 Oct 2026 00:00:00 +0000Menlo Park, CA. AttoTude's world-class engineering team works in a fast-paced, agile environment to develop next-generation baseband modems for intra-DCI applications. As a member of the system test team, the DSP Integration Test Engineer will own the bring-up, integration, and hardware maturity of high-speed DSP s coupled with AttoTude’s proprietary DiAx cable technology . The ideal candidate will be prepared to work with early…https://jobseveryhour.com/job/soc-clocking-specialist-physical-design-encharge-ai/https://jobseveryhour.com/job/soc-clocking-specialist-physical-design-encharge-ai/Wed, 28 Oct 2026 00:00:00 +0000India. We are looking for a highly skilled SoC Clocking Specialist to lead the clock architecture and physical implementation of our next-generation edge AI hardware. In this critical role, you will bridge the gap between frontend logic and backend execution, partnering directly with Architecture, RTL, and Timing teams to architect, implement, and sign-off a highly robust and power-efficient clock tree on advanced…https://jobseveryhour.com/job/senior-design-verification-engineer-ai-hardware-tenstorrent/https://jobseveryhour.com/job/senior-design-verification-engineer-ai-hardware-tenstorrent/Wed, 28 Oct 2026 00:00:00 +0000Belgrade, Serbia. Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for…https://jobseveryhour.com/job/staff-design-verification-engineer-ai-hardware-tenstorrent/https://jobseveryhour.com/job/staff-design-verification-engineer-ai-hardware-tenstorrent/Wed, 28 Oct 2026 00:00:00 +0000Belgrade, Serbia. Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for…https://jobseveryhour.com/job/physical-design-engineer-new-grad-sambanova/https://jobseveryhour.com/job/physical-design-engineer-new-grad-sambanova/Tue, 27 Oct 2026 00:00:00 +0000San Jose, California, United States. As a new grad Physical Design Engineer, you'll run and improve our RTL to GDS flow on advanced process nodes. You'll write TCL and Python scripts to automate flow steps, help physical designers debug timing and congestion issues, and work with tool vendors on bugs. Responsibilities Run synthesis and place and route using Cadence Genus, Innovus, and Cerebrus Write scripts in TCL and Python to automate and improve the…https://jobseveryhour.com/job/design-verification-engineer-new-grad-sambanova/https://jobseveryhour.com/job/design-verification-engineer-new-grad-sambanova/Tue, 27 Oct 2026 00:00:00 +0000San Jose, California, United States. As a new grad Design Verification Engineer, you'll write testbenches, tests, checkers, and coverage in SystemVerilog and UVM for RDU features. You'll run regressions, debug simulation failures, and work with RTL designers to find and fix bugs before tape-out. Responsibilities Write and execute verification plans for chip-level control and initialization features Build SystemVerilog and UVM testbench components…https://jobseveryhour.com/job/junior-emulation-engineer-celero-communications-inc/https://jobseveryhour.com/job/junior-emulation-engineer-celero-communications-inc/Tue, 27 Oct 2026 00:00:00 +0000Cordoba, Argentina. , you will help compile, run, and debug RTL on emulation systems, supporting early validation of hardware and firmware ahead of tape-out. You will work closely with RTL design, verification, and firmware teams, learn from senior engineers, and grow into an independent contributor on next-generation semiconductor products. Key Responsibilities Emulation Bring-Up: Support compilation, partitioning, and bring-up of RTL…https://jobseveryhour.com/job/technical-programme-manager-electrical-engineering-ionq/https://jobseveryhour.com/job/technical-programme-manager-electrical-engineering-ionq/Tue, 27 Oct 2026 00:00:00 +0000College Park, Maryland, United States. Role: IonQ is building quantum computers that change which problems the world can solve. Our Control Electronics team creates every custom electronic device inside an IonQ system, taking the hardware, gateware, firmware and test behind the precision control boards around the ion trap from development through to production. As Technical Programme Manager for Electrical Engineering, you will drive the team's…https://jobseveryhour.com/job/synthesis-sta-engineer-high-speed-serdes-astera-labs/https://jobseveryhour.com/job/synthesis-sta-engineer-high-speed-serdes-astera-labs/Tue, 27 Oct 2026 00:00:00 +0000San Jose, California, United States. Perform RTL synthesis, driving area, power, and timing optimization for digital controller and DSP blocks within high-speed SerDes PHY designs. Author, develop, and validate SDC constraints from scratch, including clock definitions, generated clocks, multi-frequency/multi-mode constraints, I/O delays, false paths, multicycle paths, and clock-domain crossing exceptions unique to SerDes architectures. Set up and…https://jobseveryhour.com/job/senior-design-verification-engineer-astera-labs/https://jobseveryhour.com/job/senior-design-verification-engineer-astera-labs/Tue, 27 Oct 2026 00:00:00 +0000San Jose, California, United States. As a Senior Design Verification Engineer, you will help define and deliver robust verification for next-generation connectivity silicon that enables rack-scale AI infrastructure. You will partner closely with RTL, architecture, firmware, and post-silicon teams to build verification strategies that prove complex switching behavior across high-bandwidth protocols and demanding system environments. This role offers the…https://jobseveryhour.com/job/senior-embedded-software-engineer-pure-storage/https://jobseveryhour.com/job/senior-embedded-software-engineer-pure-storage/Mon, 26 Oct 2026 00:00:00 +0000Santa Clara, California. You will join Everpure’s Datastore team to design, develop, and validate embedded firmware for our DirectFlash™ modules. In this role, you will work across firmware and hardware boundaries to build reliable, high-performance storage solutions, while also developing virtual platforms and tooling that accelerate development, debugging, and validation. You will collaborate closely with cross-functional engineering…https://jobseveryhour.com/job/principal-verification-engineer-astera-labs/https://jobseveryhour.com/job/principal-verification-engineer-astera-labs/Mon, 26 Oct 2026 00:00:00 +0000San Jose, California, United States. Lead the functional verification of advanced ASICs, including test planning, development, execution, and coverage analysis. Collaborate closely with software and system validation teams to create and execute test plans on emulation platforms. Apply both directed and constrained-random verification techniques using SystemVerilog/UVM and other relevant tools. Debug test failures, analyze coverage results, and close…https://jobseveryhour.com/job/staff-engineer-rtl-design-ai-hardware-tenstorrent/https://jobseveryhour.com/job/staff-engineer-rtl-design-ai-hardware-tenstorrent/Mon, 26 Oct 2026 00:00:00 +0000Belgrade, Serbia. to work on challenging, high-impact designs in a fast-paced environment. This role is hybrid, based out of Belgrade, Serbia. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are An engineer with a demonstrated depth in…https://jobseveryhour.com/job/senior-engineer-rtl-design-ai-hardware-tenstorrent/https://jobseveryhour.com/job/senior-engineer-rtl-design-ai-hardware-tenstorrent/Mon, 26 Oct 2026 00:00:00 +0000Belgrade, Serbia. to work on challenging, high-impact designs in a fast-paced environment. This role is hybrid, based out of Belgrade, Serbia. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are An engineer with a strong foundation in…https://jobseveryhour.com/job/director-silicon-logical-design-graphcore/https://jobseveryhour.com/job/director-silicon-logical-design-graphcore/Mon, 26 Oct 2026 00:00:00 +0000Bengaluru, India. Our team is at the forefront of the artificial intelligence revolution, enabling innovators from all industries and sectors to expand human potential with technology. The availability of specialised artificial intelligence compute will be a decisive factor in AI’s rate of progress. Graphcore allows innovators to go further, faster. What we do really makes a difference. We are looking for an experienced engineering…https://jobseveryhour.com/job/physical-design-team-lead-astera-labs/https://jobseveryhour.com/job/physical-design-team-lead-astera-labs/Sun, 25 Oct 2026 00:00:00 +0000Tel Aviv-Yafo, Tel Aviv District, Israel. Astera Labs is a hyper-growth connectivity company building the purpose-built silicon that powers rack-scale AI infrastructure. As a Principal Physical Design Engineer and Team Lead in Israel, you will lead physical design teams that take complex, high-speed mixed-signal and digital SoCs from RTL handoff through tapeout. You will set the technical direction, drive execution across multiple projects, and grow the…https://jobseveryhour.com/job/physical-design-engineering-director-astera-labs/https://jobseveryhour.com/job/physical-design-engineering-director-astera-labs/Fri, 23 Oct 2026 00:00:00 +0000Toronto, Ontario, Canada. Astera Labs is seeking a Physical Design Engineering Director to lead a team of physical design engineers at our Toronto site, driving the implementation of connectivity ASICs within our Signal Connectivity Group. This group is responsible for products that enable high-speed serial connectivity including PCIe retimers, Ethernet retimers, and signal conditioning solutions deployed across the world's largest AI…https://jobseveryhour.com/job/senior-staff-principal-software-engineer-gpu-system-software-zoox/https://jobseveryhour.com/job/senior-staff-principal-software-engineer-gpu-system-software-zoox/Thu, 22 Oct 2026 00:00:00 +0000Foster City, CA. , you will: Architect onboard GPU execution. Define how perception, prediction, and planning workloads share onboard GPUs, including scheduling, multi-tenancy, isolation, and deterministic latency under contention. Drive compute reduction. Own the multi-year roadmap to cut onboard compute per vehicle by setting latency and utilization budgets and landing the biggest levers across models, runtimes, middleware, and…https://jobseveryhour.com/job/silicon-validation-engineer-densityai/https://jobseveryhour.com/job/silicon-validation-engineer-densityai/Thu, 22 Oct 2026 00:00:00 +0000Mountain View, CA. Own silicon validation for our AI accelerator end to end. You'll start in emulation and FPGA prototyping before tapeout, bring up first silicon in the lab, and carry it through to production-quality parts in the field. You'll build the validation plans, environments, and automation that prove our silicon works at scale. You'll work closely with architecture, design, firmware, software, and systems teams to find and…https://jobseveryhour.com/job/principal-physical-design-engineer-astera-labs-2/https://jobseveryhour.com/job/principal-physical-design-engineer-astera-labs-2/Thu, 22 Oct 2026 00:00:00 +0000Bengaluru, Karnataka, India. Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software…https://jobseveryhour.com/job/senior-digital-asic-design-engineer-dsp-analog-serdes-celero-communications-inc-3/https://jobseveryhour.com/job/senior-digital-asic-design-engineer-dsp-analog-serdes-celero-communications-inc-3/Wed, 21 Oct 2026 00:00:00 +0000Ottawa, Ontario, Canada. Design and implement high-performance digital circuits and ASIC blocks using Verilog and SystemVerilog. • Develop and integrate DSP, digital communication, and high-speed SerDes functionality into complex ASIC designs. • Work closely with Analog, SerDes, DSP, Architecture, Verification, Physical Design, and Systems teams to develop and integrate mixed-signal ASICs. • Participate in the design and development of…https://jobseveryhour.com/job/senior-digital-asic-design-engineer-dsp-analog-serdes-celero-communications-inc-2/https://jobseveryhour.com/job/senior-digital-asic-design-engineer-dsp-analog-serdes-celero-communications-inc-2/Wed, 21 Oct 2026 00:00:00 +0000Irvine, CA. Design and implement high-performance digital circuits and ASIC blocks using Verilog and SystemVerilog. • Develop and integrate DSP, digital communication, and high-speed SerDes functionality into complex ASIC designs. • Work closely with Analog, SerDes, DSP, Architecture, Verification, Physical Design, and Systems teams to develop and integrate mixed-signal ASICs. • Participate in the design and development of…https://jobseveryhour.com/job/senior-digital-asic-design-engineer-dsp-analog-serdes-celero-communications-inc/https://jobseveryhour.com/job/senior-digital-asic-design-engineer-dsp-analog-serdes-celero-communications-inc/Wed, 21 Oct 2026 00:00:00 +0000San Jose, CA. Design and implement high-performance digital circuits and ASIC blocks using Verilog and SystemVerilog. • Develop and integrate DSP, digital communication, and high-speed SerDes functionality into complex ASIC designs. • Work closely with Analog, SerDes, DSP, Architecture, Verification, Physical Design, and Systems teams to develop and integrate mixed-signal ASICs. • Participate in the design and development of…https://jobseveryhour.com/job/research-engineer-chip-design-rl-anthropic/https://jobseveryhour.com/job/research-engineer-chip-design-rl-anthropic/Wed, 21 Oct 2026 00:00:00 +0000San Francisco, CA. We're hiring for the Code RL team within the RL organization. As a Research Engineer, you'll advance our models' ability to design silicon. Hardware design is difficult and unforgiving – exactly the sort of domain we want Claude to excel at. You'll leverage your chip design expertise and turn it into tasks and signals for models to learn from. Specifically, you will: Invent, design, and implement RL environments and…https://jobseveryhour.com/job/post-silicon-validation-engineer-multiple-levels-celero-communications-inc/https://jobseveryhour.com/job/post-silicon-validation-engineer-multiple-levels-celero-communications-inc/Wed, 21 Oct 2026 00:00:00 +0000Irvine, CA, or Ottawa, Ontario, Canada. Celero is seeking Post-Silicon Validation Engineers to join our validation team for next-generation coherent DSP ASICs powering AI and hyperscale optical networking. As a member of our engineering team, you will play an important role in enabling first silicon, silicon characterization, and ensuring product readiness for customer deployment and high-volume production. We are seeking multiple levels from early career…https://jobseveryhour.com/job/staff-soc-architect-graphcore/https://jobseveryhour.com/job/staff-soc-architect-graphcore/Wed, 21 Oct 2026 00:00:00 +0000Bristol, UK. Shape the high-speed interfaces and silicon sub-systems behind Graphcore’s next AI acceleration platforms. As a Staff SoC Architect in Bristol, you’ll translate product requirements into specifications for complex, highly integrated, high-performance silicon devices. You’ll own sub-system architecture, modelling, validation and evaluation, connecting early design choices with practical implementation. You’ll help…https://jobseveryhour.com/job/power-architect-ai-soc-encharge-ai/https://jobseveryhour.com/job/power-architect-ai-soc-encharge-ai/Tue, 20 Oct 2026 00:00:00 +0000India. We are seeking a critical-thinking, highly collaborative Power Architect to drive end-to-end PPA (Power, Performance, Area) excellence for our next-generation AI semiconductor chips. In this cross-functional IC role, you will bridge the gap between front-end conceptualization and back-end implementation, influencing SoC architecture, RTL design, and physical layout to deliver industry-leading power efficiency for…https://jobseveryhour.com/job/graduate-soc-architecture-engineer-2027-graphcore/https://jobseveryhour.com/job/graduate-soc-architecture-engineer-2027-graphcore/Tue, 20 Oct 2026 00:00:00 +0000Bristol, UK. Location: Bristol, UK Salary: £45,000 per annum Start date: September 2027 Application deadline : Midnight, 29th November 2026 We encourage you to apply early, as we may close applications before the advertised deadline. The Graduate Programme at Graphcore Join Graphcore in a permanent role and start your career with two years of hands-on learning. From day one, you’ll be trusted to take ownership, share your ideas…https://jobseveryhour.com/job/silicon-summer-intern-2027-graphcore/https://jobseveryhour.com/job/silicon-summer-intern-2027-graphcore/Tue, 20 Oct 2026 00:00:00 +0000Bristol, UK; Cambridge, UK. Duration: 12 weeks Salary: £2500 per month Start date: June 2027 Application deadline: Midnight 29 th November We encourage you to apply early, as we may close applications before the advertised deadline. The Internship Programme at Graphcore Explore a career at Graphcore through a 12-week summer internship, gaining hands-on experience on real projects. You’ll bring fresh ideas, put your learning into practice and…https://jobseveryhour.com/job/graduate-silicon-engineer-2027-graphcore/https://jobseveryhour.com/job/graduate-silicon-engineer-2027-graphcore/Tue, 20 Oct 2026 00:00:00 +0000Bristol, UK; Cambridge, UK. Location: Bristol or Cambridge Salary: £45,000 per annum Start date: September 2027 Application deadline: Midnight 29 th November We encourage you to apply early, as we may close applications before the advertised deadline. The Graduate Programme at Graphcore Join Graphcore in a permanent role and start your career with two years of hands-on learning. From day one, you’ll be trusted to take ownership, share your…https://jobseveryhour.com/job/senior-soc-architect-graphcore/https://jobseveryhour.com/job/senior-soc-architect-graphcore/Tue, 20 Oct 2026 00:00:00 +0000Bristol, UK. Shape the high-speed interfaces and silicon sub-systems behind Graphcore’s next AI acceleration platforms. As a Senior SoC Architect in Bristol, you’ll translate product requirements into specifications for complex, highly integrated, high-performance silicon devices. You’ll own sub-system architecture, modelling, validation and evaluation, connecting early design choices with practical implementation. You’ll help…https://jobseveryhour.com/job/staff-ml-accelerator-architect-waymo/https://jobseveryhour.com/job/staff-ml-accelerator-architect-waymo/Mon, 19 Oct 2026 00:00:00 +0000Mountain View, CA, USA; New York, New York, USA. , you will report to a Hardware Engineering Manager. You will: Analyze inference workloads and map them efficiently to hardware, proposing novel HW-friendly implementations and projecting performance Build scalable tools for performance modeling and evaluation of inference workloads Work closely with compiler and model developers to influence engineering tradeoffs and future model architectures Architect, simulate…https://jobseveryhour.com/job/applied-researcher-chip-design-primeintellect/https://jobseveryhour.com/job/applied-researcher-chip-design-primeintellect/Mon, 19 Oct 2026 00:00:00 +0000San Francisco. Applied Research at Prime We turn a workflow into tasks, environments, evaluations, and reward signals, run post-training experiments against real baselines, and deploy what works. When a result looks good, we find out whether the gain came from the model or from the data, harness, inference, or infrastructure. The reusable parts become shared research, open-source systems, and product capabilities. Every Applied…https://jobseveryhour.com/job/senior-manager-cryptographic-engineering-ionq/https://jobseveryhour.com/job/senior-manager-cryptographic-engineering-ionq/Sun, 18 Oct 2026 00:00:00 +0000Geneva, Switzerland. We are looking for a Senior Manager reporting to the Senior Manager, Hardware, to lead the people and the execution of our cryptographic engineering team. This team builds post-quantum cryptography (PQC) hardware acceleration for our quantum-safe product portfolio, targeting hardware security module (HSM) and network-appliance applications. This is a people-leadership and delivery role: you will manage and develop a…https://jobseveryhour.com/job/associate-embedded-software-engineer-anysignal/https://jobseveryhour.com/job/associate-embedded-software-engineer-anysignal/Fri, 16 Oct 2026 00:00:00 +0000Los Angeles, CA. As an Associate Embedded Software Engineer on AnySignal's Space Software team, you'll develop mission-critical embedded software for advanced radio systems supporting space and defense applications. You'll gain hands-on experience across the embedded software stack, from low-level RF integrated circuit drivers and high-speed FPGA interfaces to embedded Linux, networking, and fault-tolerant software architecture…https://jobseveryhour.com/job/director-asic-technical-program-management-astera-labs/https://jobseveryhour.com/job/director-asic-technical-program-management-astera-labs/Thu, 15 Oct 2026 00:00:00 +0000San Jose, California, United States. We are looking for a Director ASIC Technical Program Management to join the PMO organization at Astera Labs, based in the USA. In this role, you will directly manage a team of Technical Program Managers (TPMs) located across the United States. You will be responsible for mentoring and developing your team, ensuring alignment on methodology, and maintaining full visibility into program status across the portfolio…https://jobseveryhour.com/job/fpga-engineer-starshield-spacex/https://jobseveryhour.com/job/fpga-engineer-starshield-spacex/Wed, 14 Oct 2026 00:00:00 +0000Hawthorne, CA. Deliver highly reliable firmware for SpaceX-designed hardware Work with engineers across the department to develop new products, from prototype through production and flight Take ownership of your firmware products, including verification testing and writing documentation Follow the SpaceX flight software development process and write great firmware for spaceflight Work in close collaboration with avionics…https://jobseveryhour.com/job/soc-engineer-openai/https://jobseveryhour.com/job/soc-engineer-openai/Wed, 14 Oct 2026 00:00:00 +0000San Francisco. We’re looking for a SoC Engineer to help architect, design, and integrate OpenAI’s first-party AI accelerators. You will build the processor, interconnect, I/O, and platform infrastructure that connects our accelerator designs into complete, functional systems. This role combines architectural judgment with hands-on implementation. You’ll work closely with design, architecture, verification, and software teams…https://jobseveryhour.com/job/embedded-software-engineer-anysignal/https://jobseveryhour.com/job/embedded-software-engineer-anysignal/Wed, 14 Oct 2026 00:00:00 +0000Los Angeles, CA. As an Embedded Software Engineer on AnySignal's Space Software team, you'll take ownership of mission-critical embedded systems, from design and implementation through testing and deployment on customer missions. Your work will span the embedded software stack, from low-level RF integrated circuit drivers and high-speed FPGA interfaces to embedded Linux, networking, and fault-tolerant software architecture. Your…https://jobseveryhour.com/job/teach-lead-physical-design-engineer-astera-labs/https://jobseveryhour.com/job/teach-lead-physical-design-engineer-astera-labs/Tue, 13 Oct 2026 00:00:00 +0000Singapore, Singapore. We are seeking a Senior Physical Design Engineer to join our high-performance design team working on next-generation transceiver IPs targeting the TSMC 3nm and advanced technology nodes Key Responsibilities Perform block-level and top-level physical implementation including floorplanning, placement, clock tree synthesis (CTS), routing, and physical verification for high-speed designs in advanced technology nodes…https://jobseveryhour.com/job/principal-physical-design-engineer-astera-labs/https://jobseveryhour.com/job/principal-physical-design-engineer-astera-labs/Tue, 13 Oct 2026 00:00:00 +0000Singapore, Singapore. We are seeking a Senior Physical Design Engineer to join our high-performance design team working on next-generation transceiver IPs targeting the TSMC 3nm and advanced technology nodes Key Responsibilities Perform block-level and top-level physical implementation including floorplanning, placement, clock tree synthesis (CTS), routing, and physical verification for high-speed designs in advanced technology nodes…https://jobseveryhour.com/job/analog-mixed-signal-design-engineer-astera-labs/https://jobseveryhour.com/job/analog-mixed-signal-design-engineer-astera-labs/Tue, 13 Oct 2026 00:00:00 +0000Singapore, Singapore. As an Analog/Mixed-Signal IC Design Engineer , you will be part of a key team designing sophisticated advanced node CMOS products. Your responsibilities will include developing and verifying circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, and CDRs to meet performance targets. You will also work on analog and clocking blocks for connectivity applications, using industry-standard tools like Spectre and…https://jobseveryhour.com/job/tech-lead-analog-mixed-signal-ic-layout-engineer-astera-labs/https://jobseveryhour.com/job/tech-lead-analog-mixed-signal-ic-layout-engineer-astera-labs/Tue, 13 Oct 2026 00:00:00 +0000Singapore, Singapore. Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software…https://jobseveryhour.com/job/senior-analog-mixed-signal-ic-layout-engineer-astera-labs/https://jobseveryhour.com/job/senior-analog-mixed-signal-ic-layout-engineer-astera-labs/Tue, 13 Oct 2026 00:00:00 +0000Singapore, Singapore. Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software…https://jobseveryhour.com/job/senior-software-engineer-full-stack-development-blackstone-eit/https://jobseveryhour.com/job/senior-software-engineer-full-stack-development-blackstone-eit/Tue, 13 Oct 2026 00:00:00 +0000Dubai, Dubai, United Arab Emirates. Portal Development: Develop and maintain Next.js e-services, including application forms, document uploads, request tracking, payment journeys and customer account functions. • Website and CMS: Develop React/ Next.js website features and configure Strapi content types, components, permissions, publishing workflows and API integration. • Backend Development: Develop and maintain Node.js services and middleware…https://jobseveryhour.com/job/principal-physical-design-engineer-astera-labs-4/https://jobseveryhour.com/job/principal-physical-design-engineer-astera-labs-4/Mon, 12 Oct 2026 00:00:00 +0000Ahmedabad, Gujarat, India. Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software…https://jobseveryhour.com/job/principal-physical-design-cad-engineer-astera-labs-2/https://jobseveryhour.com/job/principal-physical-design-cad-engineer-astera-labs-2/Sun, 11 Oct 2026 00:00:00 +0000Haifa District, Israel. Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, We are looking for a Physical Design CAD Engineer with at least 3 years of hands-on experience in digital implementation flows. The ideal candidate is highly technical, curious, and…https://jobseveryhour.com/job/sr-asic-design-engineer-silicon-engineering-spacex/https://jobseveryhour.com/job/sr-asic-design-engineer-silicon-engineering-spacex/Fri, 09 Oct 2026 00:00:00 +0000Palo Alto, CA. , you will be developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network. RESPONSIBILITIES: Evaluate architectural trade-offs…https://jobseveryhour.com/job/asic-design-engineer-silicon-engineering-spacex/https://jobseveryhour.com/job/asic-design-engineer-silicon-engineering-spacex/Fri, 09 Oct 2026 00:00:00 +0000Palo Alto, CA. , you will be developing cutting-edge next-generation FPGAs and ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network. RESPONSIBILITIES: Design ASICs and/or…https://jobseveryhour.com/job/physical-design-engineer-sk-hynix-memory-solutions-america-inc/https://jobseveryhour.com/job/physical-design-engineer-sk-hynix-memory-solutions-america-inc/Wed, 07 Oct 2026 00:00:00 +0000San Jose. Join our Physical Design (SoC Integration) team responsible for delivering high-performance SoC designs from RTL to GDS. As a Sr. Staff Physical Design Engineer, you will lead physical implementation efforts for advanced-node designs, driving critical blocks through synthesis, placement, CTS, routing, and signoff. You will work closely with front-end, DFT, power, and analog teams to optimize PPA (Power, Performance…https://jobseveryhour.com/job/senior-asic-rtl-design-engineer-ai-hardware-cerebras/https://jobseveryhour.com/job/senior-asic-rtl-design-engineer-ai-hardware-cerebras/Wed, 07 Oct 2026 00:00:00 +0000Sunnyvale, CA. As a senior front-end design engineer, you will be a key part of the world-class team designing and developing the next generations of the Cerebras Wafer Scale Engine (WSE). This role requires deep expertise in RTL design and integration, with a strong focus on delivering high-performance, power-efficient, and scalable solutions. You will collaborate closely with the design verification, physical design, software…https://jobseveryhour.com/job/digital-asic-design-engineer-attotude/https://jobseveryhour.com/job/digital-asic-design-engineer-attotude/Wed, 07 Oct 2026 00:00:00 +0000Nuremberg, Germany. We are seeking an experienced Digital IC Design Engineer to join our growing team. In this role, you will be part of an experienced design team developing cutting-edge DSP and mixed-signal ICs. This is a hands-on technical position that requires in-depth technical expertise, and the ability to work in a team of highly experienced engineers to accomplish the goals. Key Responsibilities Flow system level requirements…https://jobseveryhour.com/job/datacenter-agentic-ai-workload-performance-optimization-engi-tenstorrent/https://jobseveryhour.com/job/datacenter-agentic-ai-workload-performance-optimization-engi-tenstorrent/Mon, 05 Oct 2026 00:00:00 +0000Santa Clara, California, United States; Toronto, Ontario, Canada. Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for…https://jobseveryhour.com/job/formal-verification-engineer-tenstorrent/https://jobseveryhour.com/job/formal-verification-engineer-tenstorrent/Mon, 05 Oct 2026 00:00:00 +0000Santa Clara, California, United States; Spain. Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for…https://jobseveryhour.com/job/research-scientist-loop-engineering-and-ai-infrastructure-sk-hynix-memory-solutions-america-inc/https://jobseveryhour.com/job/research-scientist-loop-engineering-and-ai-infrastructure-sk-hynix-memory-solutions-america-inc/Fri, 02 Oct 2026 00:00:00 +0000San Jose. We are hiring a full-time research scientist. Depending on your qualifications, the job is loop engineering, AI infrastructure research, or both. Loop engineering is the design and study of closed-loop flows that automate, optimize, and explore SoC designs. These are AI-assisted hardware/software co-design flows. CHIA, from UC Berkeley, is one example of a framework you may use. AI infrastructure research is…