🇺🇸RTL design jobs in California
186 open roles mentioning RTL design in California as of Nov 15, 2026. Tenstorrent, Astera Labs, SpaceX, Astranis and Cerebras have the most. The median advertised salary is $215K.
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Skills asked for in RTL design roles in California
Job titles in RTL design roles in California
Bars show the share of these 186 roles; one role can count in several rows.
- Senior FPGA Verification EngineerAnduril Industries · 🇺🇸Goleta, California, United States$191K - $254KSeniorPythonC++Linux
- Staff Engineer, Digital ASIC Design — Storage ControllersSK hynix memory solutions America Inc. · 🇺🇸San Jose—Lead and aboveMachine LearningVerilogStorage systems
- RTL Design Engineer, Networking / NoCOpenAI · 🇺🇸San Francisco$287K - $485KHybridVerilogHigh-performance computingASIC
- Engineer, CPU Performance VerificationTenstorrent · 🇺🇸Austin, Texas, United States; Santa Clara, California, Un…—PythonC++Compilers
- Principal Design Verification Engineer (AI Fabric Switches)Astera Labs · 🇺🇸San Jose, California, United States$185K - $240KLead and abovePythonC++AI
- Sr/Staff Digital Design EngineerLightmatter · 🇺🇸Mountain View, CA$164K - $222KLead and abovePythonBashVerilog
- Physical Design and CAD EngineerAstera Labs · 🇺🇸San Jose, California, United States$160K - $200KPythonHardware interfacesCompilers
- DFT EngineerTenstorrent · 🇺🇸Austin, Texas, United States; Fort Collins, Colorado, Uni… · +1 more location—VerilogHardware interfacesCompilers
- Principal Design EngineerAstera Labs · 🇺🇸San Jose, California, United States$185K - $240KLead and abovePythonFirmwareHardware interfaces
- Silicon Design LeadOpenAI · 🇺🇸San Francisco$287K - $485KHybridLead and aboveVerilogThreat modelingFirmware
- Staff Cloud Hypervisor Engineer, ComputeCrusoe · 🇺🇸Sunnyvale, CA - US$215K - $260KLead and aboveRustC++Linux
- Principal PCS/PMA RTL Design EngineerAstera Labs · 🇺🇸San Jose, California, United States$185K - $240KLead and abovePythonVerilogPerl
- EDA Cloud & Developer Infrastructure EngineerOpenAI · 🇺🇸San Francisco$287K - $485KHybridPythonPostgreSQLTerraform
- Technical Lead Digital Design EngineerAstera Labs · 🇺🇸San Jose, California, United States$160K - $200KLead and abovePythonVerilogTest planning
- Electrical Engineer- SDR HardwareAstranis · 🇺🇸San Francisco$115K - $180KPythonPCB designAnalog design
- DSP Integration Test EngineerAttoTude · 🇺🇸Menlo Park, CA—PythonC++Docker
- Physical Design Engineer, New GradSambaNova · 🇺🇸San Jose, California, United States$120K - $150KJuniorPythonPerlTest planning
- Design Verification Engineer, New GradSambaNova · 🇺🇸San Jose, California, United States$120K - $150KJuniorPythonVerilogPerl
- Synthesis & STA Engineer – High-Speed SerDesAstera Labs · 🇺🇸San Jose, California, United States$160K - $200KPythonVerilogPerl
- Senior Design Verification EngineerAstera Labs · 🇺🇸San Jose, California, United States · +1 more location$148K - $165KSeniorPythonVerilogPerl
- Senior Embedded Software EngineerPure Storage · 🇺🇸Santa Clara, California$202K - $248KSeniorPythonC++Linux
- Principal Verification EngineerAstera Labs · 🇺🇸San Jose, California, United States · +1 more location$185K - $230KLead and abovePythonC++Verilog
- Senior Staff/Principal Software Engineer - GPU System Software, Onboard ExecutionZoox · 🇺🇸Foster City, CA$339K - $455KLead and aboveC++LinuxCUDA
- Silicon Validation EngineerDensityAI · 🇺🇸Mountain View, CA$250K - $300KPythonC++Firmware
- Senior Digital ASIC Design Engineer - DSP/Analog/SerDesCelero Communications, Inc. · 🇺🇸Irvine, CA · +1 more location$150K - $250KSeniorPythonMATLABVerilog
- Research Engineer, Chip Design RLAnthropic · 🇺🇸San Francisco, CA$500K - $850KLLMReinforcement learningASIC
- Post-Silicon Validation Engineer (Multiple Levels)Celero Communications, Inc. · 🇺🇸🇨🇦Irvine, CA, or Ottawa, Ontario, CanadaCA$100K - CA$200KPythonLoad testingFirmware
- Staff ML Accelerator ArchitectWaymo · 🇺🇸Mountain View, CA, USA; New York, New York, USA$251K - $310KLead and aboveMachine LearningVerilogCompilers
- Applied Researcher - Chip DesignPrimeIntellect · 🇺🇸San Francisco—PythonLangChainDatadog
- Associate Embedded Software EngineerAnysignal · 🇺🇸Los Angeles, CA$110K - $145KJuniorPythonC++Linux
- Director ASIC Technical Program ManagementAstera Labs · 🇺🇸San Jose, California, United States$210K - $275KLead and aboveFirmwareHardware interfacesASIC
- FPGA Engineer (Starshield)SpaceX · 🇺🇸Hawthorne, CA$125K - $160KPythonC++Bash
- SoC EngineerOpenAI · 🇺🇸San Francisco$287K - $485KHybridVerilogFirmwareHardware interfaces
- Embedded Software EngineerAnysignal · 🇺🇸Los Angeles, CA$130K - $165KPythonC++Linux
- Sr. ASIC Design Engineer (Silicon Engineering)SpaceX · 🇺🇸Palo Alto, CA · +1 more location$175K - $280KSeniorPythonVerilogFirmware
- ASIC Design Engineer (Silicon Engineering)SpaceX · 🇺🇸Palo Alto, CA$135K - $175KPythonC++Bash
- Physical Design EngineerSK hynix memory solutions America Inc. · 🇺🇸San Jose—PythonMachine LearningPerl
- Senior ASIC RTL Design Engineer, AI HardwareCerebras · 🇺🇸Sunnyvale, CA$200K - $290KHybridSeniorPython.NETMachine Learning
- Datacenter & Agentic AI Workload Performance Optimization EngineerTenstorrent · 🇺🇸🇨🇦Santa Clara, California, United States; Toronto, Ontario…—RustGoPython
- Formal Verification EngineerTenstorrent · 🇺🇸🇪🇸Santa Clara, California, United States; Spain—PythonC++Verilog
- Research Scientist - Loop Engineering and AI InfrastructureSK hynix memory solutions America Inc. · 🇺🇸San Jose—PythonMachine LearningAI
- Datacenter & Agentic AI Workload Performance Analysis EngineerTenstorrent · 🇺🇸Santa Clara, California, United States—PythonC++Linux
- FPGA/ASIC Design Engineer (Silicon Engineering)SpaceX · 🇺🇸Irvine, CA$125K - $160KPythonC++Bash
- Tech Lead, Digital Design EngineerAstera Labs · 🇺🇸San Jose, California, United States$176K - $195KLead and abovePythonHardware interfacesASIC
- Design Verification Emulation, HardwareRiver AI Inc. · 🇺🇸Austin, TX, Palo Alto, CA$200K - $420KPythonC++CI/CD
- Tech Lead Engineer, Design VerificationAstera Labs · 🇺🇸San Jose, California, United States$176K - $195KLead and abovePythonVerilogPowerShell
- Staff Engineer, Post-Silicon ValidationTenstorrent · 🇺🇸Austin, Texas, United States; Santa Clara, California, Un…—Lead and aboveLinuxFirmwareCompilers
- Sr. Staff / Principal Physical Design EngineerSK hynix memory solutions America Inc. · 🇺🇸San Jose—Lead and abovePythonMachine LearningPerl
- Sr. Engineer, Performance Infrastructure (RISC-V)Tenstorrent · 🇦🇺🇺🇸Australia; Santa Clara, California, United States—SeniorPythonLinuxShell scripting
- FPGA Associate (Winter 2027)Astranis · 🇺🇸San Francisco—VerilogFPGARTL design
Showing the newest 50. See all 186 in search
Who is hiring for RTL design roles in California
What RTL design roles in California pay, by level
| Level in the title | Median advertised salary | Roles counted |
|---|---|---|
| No level in the title | $215K | 53 |
| Senior | $200K | 31 |
| Lead and above | $228K | 43 |
Medians of the midpoints of advertised yearly US-dollar ranges; a level needs at least 15 such roles. Advertised, not verified pay.
Questions about RTL design jobs in California
- How many RTL design jobs in California are open right now?
- There are 186 open RTL design jobs in California at 29 companies on Jobs Every Hour as of Nov 15, 2026. 4 of them were posted in the last seven days. The list is rebuilt every hour from the employers' own careers pages.
- Which companies have the most RTL design jobs in California?
- Right now the most openings are at Tenstorrent (31), Astera Labs (25), SpaceX (17), Astranis (13) and Cerebras (11). The ranking changes as companies open and close roles.
- Are there remote RTL design jobs in California?
- None of the 186 open RTL design jobs in California are listed as remote at the moment. Remote roles appear here as soon as employers post them.
- What do RTL design jobs in California pay?
- The median advertised salary is $215K, based on 130 open roles that publish a yearly US-dollar range. The middle half of those roles advertise between $180K and $255K. These are advertised ranges, not verified pay. Most employers here are technology companies, so the figures run above the wider market for the same work.
- Is it hard to get one of the RTL design jobs in California?
- 6 of the 186 open RTL design jobs in California (3%) are for beginners: junior roles and internships. Of the 133 postings that state experience, the median asks for 5 years. 29 companies are hiring and 4 roles were posted in the last seven days. Matching your resume to the skills each posting names helps most; the free resume builder shows the match.
- How is AI changing RTL design jobs in California?
- 45 of the 186 open RTL design jobs in California (24%) ask for AI or machine-learning skills, most often Machine Learning, AI, Computer Vision. Employers still list 186 such roles today at 29 companies. Counted from the postings' own text on Nov 15, 2026.
- What skills do RTL design jobs in California ask for?
- Most often RTL design (100%), Python (68%), ASIC (61%), Verilog (45%), SystemVerilog (41%) of the 186 open postings, counted from their own text on Nov 15, 2026.
- Which job titles come up most in RTL design jobs in California?
- Physical Design Engineer (12), Design Verification Engineer (7), Senior FPGA Engineer (6), FPGA Engineer (4), Principal Physical Design Engineer (4): the most common titles among the 186 open roles, without the level and place notes in brackets.
- Are RTL design jobs in California in demand in 2026?
- 186 RTL design jobs in California are open on Jobs Every Hour today at 29 companies, 0.1% of all 148,162 open jobs here; 4 were posted in the last seven days. The median advertised salary is $215K. 0 (0%) can be done remotely.
- How do I apply for RTL design jobs in California?
- Open a job and press “Apply on company site”. You go straight to the employer's own careers page and apply there. Jobs Every Hour needs no account and charges nothing for applying.
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