Design Verification Tech Lead- SerDes/PHY IP is open at Astera Labs in San Jose, California, United States. The posting gives a salary of $160K - $200K. Posted on Sep 21, 2026, and still on Astera Labs’s careers page when we last checked, on Nov 14, 2026.
About the role
Astera Labs is hiring a Principal Design Verification Engineer to own functional verification of our high-speed SerDes/PHY IP — the connectivity engine powering rack-scale AI infrastructure. You will architect verification environments, drive coverage closure, and ensure first-pass silicon success on the analog/digital boundary that defines next-generation AI systems. This is a high-impact, hands-on role at the…
The opening lines of the posting. The rest is on Astera Labs’s careers page.
Hiring at Astera Labs
Astera Labs has 173 open roles right now. Most are in Engineering, Design and Supply Chain & Logistics. The median advertised salary across its roles with a published range is $212K. See all its roles
