https://jobseveryhour.com/skills/systemverilog/SystemVerilog jobs — Jobs Every HourSun, 15 Nov 2026 19:27:35 +0000https://jobseveryhour.com/job/principal-design-verifiction-engineer-sambanova/https://jobseveryhour.com/job/principal-design-verifiction-engineer-sambanova/Fri, 13 Nov 2026 00:00:00 +0000San Jose, California, United States. Define and own the verification execution plan end to end for a major subsystem of the RDU — test plan, testbench architecture, coverage model, formal verification, and sign-off criteria Serve as the technical authority for verification of your subsystem: review and arbitrate testbench design decisions, and lead debug on the hardest failures Verify functional and performance behavior Build the coverage model for…https://jobseveryhour.com/job/senior-fpga-verification-engineer-anduril-industries-3/https://jobseveryhour.com/job/senior-fpga-verification-engineer-anduril-industries-3/Fri, 13 Nov 2026 00:00:00 +0000Waltham, Massachusetts, United States. The Imaging team is seeking a Senior FPGA Verification Engineer to help design a new product lines. In this role, you will work closely with an interdisciplinary technical team to define, complete the design and analysis, build prototypes leading to ground and flight testing, and mature the prototypes into products. WHAT YOU’LL DO Verification environment architecture and design using tools like SystemVerilog or…https://jobseveryhour.com/job/senior-fpga-verification-engineer-anduril-industries/https://jobseveryhour.com/job/senior-fpga-verification-engineer-anduril-industries/Fri, 13 Nov 2026 00:00:00 +0000Goleta, California, United States. The Imaging team is seeking a Senior FPGA Verification Engineer to help design a new product lines. In this role, you will work closely with an interdisciplinary technical team to define, complete the design and analysis, build prototypes leading to ground and flight testing, and mature the prototypes into products. WHAT YOU’LL DO Verification environment architecture and design using tools like SystemVerilog or…https://jobseveryhour.com/job/senior-fpga-verification-engineer-anduril-industries-2/https://jobseveryhour.com/job/senior-fpga-verification-engineer-anduril-industries-2/Fri, 13 Nov 2026 00:00:00 +0000Boulder, Colorado, United States. The Imaging team is seeking a Senior FPGA Verification Engineer to help design a new product lines. In this role, you will work closely with an interdisciplinary technical team to define, complete the design and analysis, build prototypes leading to ground and flight testing, and mature the prototypes into products. WHAT YOU’LL DO Verification environment architecture and design using tools like SystemVerilog or…https://jobseveryhour.com/job/senior-firmware-engineer-anduril-industries/https://jobseveryhour.com/job/senior-firmware-engineer-anduril-industries/Fri, 13 Nov 2026 00:00:00 +0000Waltham, Massachusetts, United States. The Imaging team is seeking a Senior Firmware Engineer to design a new product lines. In this role, you will work closely with an interdisciplinary technical team to define, complete the design and analysis, build prototypes leading to ground and flight testing, and mature the prototypes into products. WHAT YOU’LL DO Lead FPGA architecture, standards, development and review processes FPGA Development : Designing…https://jobseveryhour.com/job/senior-embedded-engineer-anduril-industries/https://jobseveryhour.com/job/senior-embedded-engineer-anduril-industries/Fri, 13 Nov 2026 00:00:00 +0000Waltham, Massachusetts, United States. The Imaging team is seeking a Senior Embedded Engineer to design a new product lines. In this role, you will work closely with an interdisciplinary technical team to define, complete the design and analysis, build prototypes leading to ground and flight testing, and mature the prototypes into products. WHAT YOU’LL DO Lead FPGA architecture, standards, development and review processes FPGA Development : Designing…https://jobseveryhour.com/job/fpga-engineering-intern-summer-2027-reliable-robotics/https://jobseveryhour.com/job/fpga-engineering-intern-summer-2027-reliable-robotics/Fri, 13 Nov 2026 00:00:00 +0000Mountain View, CA. In your role as a FPGA Design intern, you will work in a highly collaborative and cross-functional development environment including mutual peer review to maintain high product quality. This work will include FPGA design, synthesis, simulation, hardware integration, and verification. You will contribute to multiple FPGA projects in support of the long-term Reliable Robotics technology roadmap. BASIC SUCCESS CRITERIA…https://jobseveryhour.com/job/fpga-engineer-anysignal/https://jobseveryhour.com/job/fpga-engineer-anysignal/Thu, 12 Nov 2026 00:00:00 +0000Los Angeles, CA. As an FPGA Engineer on the Space team, you will be responsible for designing and building the gateware at the heart of our next generation of space radios and RF solutions. Your work will span all aspects of the FPGA system required to create a full product, from high-speed interfaces with hardware components to tight integration with the software layer. Your focus, however, will be the implementation of the digital…https://jobseveryhour.com/job/senior-fpga-prototyping-engineer-k2-space-2/https://jobseveryhour.com/job/senior-fpga-prototyping-engineer-k2-space-2/Wed, 11 Nov 2026 00:00:00 +0000United States - Remote. We are seeking a Senior FPGA & Silicon Bring-up Engineer to accelerate the development of next-generation communications ASICs. You will own FPGA prototyping, firmware enablement, first-silicon bring-up, and hardware validation, serving as the bridge between ASIC design, firmware, software, and system integration. This role spans the entire silicon lifecycle from pre-silicon FPGA platforms that enable early…https://jobseveryhour.com/job/senior-asic-design-verification-engineer-k2-space/https://jobseveryhour.com/job/senior-asic-design-verification-engineer-k2-space/Wed, 11 Nov 2026 00:00:00 +0000United States - Remote. We are seeking a Senior ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ownership, deep technical…https://jobseveryhour.com/job/principal-asic-design-verification-engineer-k2-space/https://jobseveryhour.com/job/principal-asic-design-verification-engineer-k2-space/Wed, 11 Nov 2026 00:00:00 +0000United States - Remote. We are seeking a Principal ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ownership, deep technical…https://jobseveryhour.com/job/senior-hardware-design-engineer-arago/https://jobseveryhour.com/job/senior-hardware-design-engineer-arago/Wed, 11 Nov 2026 00:00:00 +0000Paris Offices. Design and verify custom digital hardware components and architectures that enable high-performance, tightly integrated computation workloads and interface Arago’s custom tensor unit for advanced AI/ML applications. RESPONSIBILITIES - Design, implement, and verify RTL blocks for memory, control, and compute subsystems within Arago’s custom multiphysics computation unit. - Collaborate with Arago’s system software and…https://jobseveryhour.com/job/staff-engineer-digital-asic-design-storage-controllers-sk-hynix-memory-solutions-america-inc/https://jobseveryhour.com/job/staff-engineer-digital-asic-design-storage-controllers-sk-hynix-memory-solutions-america-inc/Tue, 10 Nov 2026 00:00:00 +0000San Jose. Join our digital ASIC design team to develop IP for next-generation SSD controllers and storage solutions. This role offers opportunities across the controller architecture, including host interfaces, on-chip interconnects, and back-end NAND subsystems. You will translate product requirements into microarchitecture specifications, implement high-quality RTL, and collaborate with verification and physical design…https://jobseveryhour.com/job/rtl-design-engineer-networking-noc-openai/https://jobseveryhour.com/job/rtl-design-engineer-networking-noc-openai/Tue, 10 Nov 2026 00:00:00 +0000San Francisco. We’re looking for an RTL Design Engineer to help design and develop next-generation AI accelerator silicon. In this role, you'll work across architecture, microarchitecture, and RTL implementation, translating complex system and performance requirements into efficient, scalable hardware designs. You'll collaborate closely with silicon architects, hardware and software engineers, verification, and physical design…https://jobseveryhour.com/job/principal-design-verification-engineer-ai-fabric-switches-astera-labs/https://jobseveryhour.com/job/principal-design-verification-engineer-ai-fabric-switches-astera-labs/Sat, 07 Nov 2026 00:00:00 +0000San Jose, California, United States. Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software…https://jobseveryhour.com/job/sr-staff-digital-design-engineer-lightmatter-3/https://jobseveryhour.com/job/sr-staff-digital-design-engineer-lightmatter-3/Fri, 06 Nov 2026 00:00:00 +0000Toronto, ON. Develop RTL (i.e. system Verilog) modules with DFT considerations for IC development Debug complex logic and mixed signal simulations Understand and integrate silicon photonic communication and compute technology into digital accelerator design Actively work with Architecture, Design Verification, Physical Design, Photonic, Analog and Software teams to realize high performance, low power designs in advanced…https://jobseveryhour.com/job/sr-staff-digital-design-engineer-lightmatter-2/https://jobseveryhour.com/job/sr-staff-digital-design-engineer-lightmatter-2/Fri, 06 Nov 2026 00:00:00 +0000Boston, MA. Develop RTL (i.e. system Verilog) modules with DFT considerations for IC development Debug complex logic and mixed signal simulations Understand and integrate silicon photonic communication and compute technology into digital accelerator design Actively work with Architecture, Design Verification, Physical Design, Photonic, Analog and Software teams to realize high performance, low power designs in advanced…https://jobseveryhour.com/job/sr-staff-digital-design-engineer-lightmatter/https://jobseveryhour.com/job/sr-staff-digital-design-engineer-lightmatter/Fri, 06 Nov 2026 00:00:00 +0000Mountain View, CA. Develop RTL (i.e. system Verilog) modules with DFT considerations for IC development Debug complex logic and mixed signal simulations Understand and integrate silicon photonic communication and compute technology into digital accelerator design Actively work with Architecture, Design Verification, Physical Design, Photonic, Analog and Software teams to realize high performance, low power designs in advanced…https://jobseveryhour.com/job/validation-and-verification-engineer-aviation-engineering-skyryse/https://jobseveryhour.com/job/validation-and-verification-engineer-aviation-engineering-skyryse/Fri, 06 Nov 2026 00:00:00 +0000El Segundo, CA. , you will be responsible for the verification, validation, and quality assurance of Fly-by-Wire software, Display software, and FPGA firmware. You will create, execute, review tests at the high-level and low-level requirement levels, including FPGA requirements-based verification through simulation and hardware testing. You will also review requirements, design, code, and HDL using checklists. The ideal candidate…https://jobseveryhour.com/job/dft-engineer-tenstorrent-2/https://jobseveryhour.com/job/dft-engineer-tenstorrent-2/Fri, 06 Nov 2026 00:00:00 +0000Austin, Texas, United States; Fort Collins, Colorado, United States; Santa Clara, California, United States. is Design for Test (DFT) for high-performance designs going into industry leading AI/ML architectures. The person coming into this role will be involved in all implementation aspects from RTL to tapeout for various IPs on the chip. High level challenges include reducing test cost while attaining high coverage, and facilitating debug and yield learnings while minimizing design intrusions. The work is done…https://jobseveryhour.com/job/fpga-engineer-tomorrow-io/https://jobseveryhour.com/job/fpga-engineer-tomorrow-io/Fri, 06 Nov 2026 00:00:00 +0000Golden, Colorado, United States. , you will translate high level design requirements into concrete digital logic designs and contribute to the development of our custom electronic hardware. You will join a collaborative, high-performing environment that values technical excellence, shared accountability, and the pursuit of ambitious, mission-driven engineering goals. PLEASE NOTE: This position requires access to technology that is controlled under…https://jobseveryhour.com/job/principal-formal-verification-engineer-astera-labs/https://jobseveryhour.com/job/principal-formal-verification-engineer-astera-labs/Thu, 05 Nov 2026 00:00:00 +0000Bengaluru, Karnataka, India. We are looking for a Principal Formal Verification Engineer with 10+ years of experience to lead formal verification efforts for complex semiconductor and silicon designs. This role will be responsible for driving verification strategy, improving design quality, and mentoring engineers while working closely with design, architecture, and validation teams. Key Responsibilities Lead formal verification activities for…https://jobseveryhour.com/job/silicon-design-lead-openai/https://jobseveryhour.com/job/silicon-design-lead-openai/Wed, 04 Nov 2026 00:00:00 +0000San Francisco. We’re looking for a Silicon Design Lead to drive architecture, microarchitecture, and implementation of key IP and subsystems for our AI hardware platforms. You will translate functional, performance, and security requirements into efficient silicon designs, owning technical decisions from architectural definition through implementation and integration. Part of this role will focus on hardware security…https://jobseveryhour.com/job/mixed-signal-ic-design-engineer-arago/https://jobseveryhour.com/job/mixed-signal-ic-design-engineer-arago/Wed, 04 Nov 2026 00:00:00 +0000Paris Offices. Design, integrate, and deliver high-performance digital subsystems within mixed-signal ICs, enabling control, calibration, and high-speed data movement in analog-centric environments — owning the flow from RTL to physical implementation and tape-out. RESPONSIBILITIES - Design and verify digital subsystems that interface directly with high-speed analog and mixed-signal circuits — including calibration engines…https://jobseveryhour.com/job/principal-pcs-pma-rtl-design-engineer-astera-labs/https://jobseveryhour.com/job/principal-pcs-pma-rtl-design-engineer-astera-labs/Tue, 03 Nov 2026 00:00:00 +0000San Jose, California, United States. PCS/PMA RTL design and implementation Develop synthesizable Verilog/SystemVerilog RTL for PCS and PMA digital blocks supporting Ethernet, PCIe, UCIe, UALink, and related protocols. Implement PCS functions such as line encoding/decoding (64b/66b, 128b/130b, 8b/10b), scrambling/descrambling, block and word alignment, lane deskew and reordering, gearboxes, elastic buffers/FIFOs, and rate adaptation. Implement forward…https://jobseveryhour.com/job/fpga-design-engineer-r5347-shield-ai-2/https://jobseveryhour.com/job/fpga-design-engineer-r5347-shield-ai-2/Tue, 03 Nov 2026 00:00:00 +0000Seattle, WA, US. We are seeking a highly motivated FPGA Design Engineer with experience developing high-performance digital designs. The ideal candidate will be responsible for designing, implementing, verifying, and debugging FPGA-based solutions for complex avionics solutions for cutting-edge Unmanned Aerial Vehicles (UAV). This role requires strong digital design fundamentals, experience with AMD/Xilinx development tools, and the…https://jobseveryhour.com/job/software-engineer-embedded-applications-r5068-shield-ai-2/https://jobseveryhour.com/job/software-engineer-embedded-applications-r5068-shield-ai-2/Tue, 03 Nov 2026 00:00:00 +0000Dallas, TX, US. We are seeking skilled, experienced embedded software engineers with relevant experience in C++ in embedded systems to join our X-BAT Embedded Software Team focused on developing complex avionics software that merges hardware and embedded applications for cutting-edge Unmanned Aerial Vehicles (UAV). The Embedded Software Engineer works with in a high pace environment with a cross-functional team of program…https://jobseveryhour.com/job/technical-lead-digital-design-engineer-astera-labs/https://jobseveryhour.com/job/technical-lead-digital-design-engineer-astera-labs/Mon, 02 Nov 2026 00:00:00 +0000San Jose, California, United States. Own the RTL implementation of complex digital designs from micro-architecture through sign-off. Collaborate with verification teams to review test plans and debug issues. Support efforts to achieve timing closure and implement Design-for-Test (DFT) features. Scripting and automation for ASIC methodology improvement. Accountable for quality and overall design success with the support of senior engineers. Required…https://jobseveryhour.com/job/staff-principal-asic-design-engineer-astera-labs/https://jobseveryhour.com/job/staff-principal-asic-design-engineer-astera-labs/Sun, 01 Nov 2026 00:00:00 +0000Haifa District, Israel. Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Staff / Principal ASIC Design Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful…https://jobseveryhour.com/job/senior-asic-design-engineer-astera-labs/https://jobseveryhour.com/job/senior-asic-design-engineer-astera-labs/Sun, 01 Nov 2026 00:00:00 +0000Haifa District, Israel. Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Senior ASIC Design Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful product…https://jobseveryhour.com/job/hardware-engineers-rtl-implementation-and-evaluation-workflo-terac/https://jobseveryhour.com/job/hardware-engineers-rtl-implementation-and-evaluation-workflo-terac/Sat, 31 Oct 2026 00:00:00 +0000United States. Walk us through your approach to RTL implementation and hardware description - Review and react to specific automated evaluation scenarios - Describe a recent time you tackled a complex hardware verification challenge - Provide feedback on current workflows and tooling gaps WHO SHOULD APPLY - Professional experience in hardware engineering or RTL design - Hands-on background with hardware description languages…https://jobseveryhour.com/job/fpga-engineer-anduril-industries/https://jobseveryhour.com/job/fpga-engineer-anduril-industries/Sat, 31 Oct 2026 00:00:00 +0000Broomfield, Colorado, United States; Fort Collins, Colorado, United States. , you will work closely with an interdisciplinary technical team to define FPGA designs, determine solutions, build prototypes, perform testing, and mature the prototypes into products. About the Job We are looking for an FPGA Engineer to join our growing team in Fort Collins, CO. You will develop and verify FPGA designs that control radar hardware, move high-rate sensor data, and support real-time signal…https://jobseveryhour.com/job/senior-design-verification-engineer-ai-hardware-tenstorrent/https://jobseveryhour.com/job/senior-design-verification-engineer-ai-hardware-tenstorrent/Wed, 28 Oct 2026 00:00:00 +0000Belgrade, Serbia. Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for…https://jobseveryhour.com/job/design-verification-engineer-new-grad-sambanova/https://jobseveryhour.com/job/design-verification-engineer-new-grad-sambanova/Tue, 27 Oct 2026 00:00:00 +0000San Jose, California, United States. As a new grad Design Verification Engineer, you'll write testbenches, tests, checkers, and coverage in SystemVerilog and UVM for RDU features. You'll run regressions, debug simulation failures, and work with RTL designers to find and fix bugs before tape-out. Responsibilities Write and execute verification plans for chip-level control and initialization features Build SystemVerilog and UVM testbench components…https://jobseveryhour.com/job/junior-emulation-engineer-celero-communications-inc/https://jobseveryhour.com/job/junior-emulation-engineer-celero-communications-inc/Tue, 27 Oct 2026 00:00:00 +0000Cordoba, Argentina. , you will help compile, run, and debug RTL on emulation systems, supporting early validation of hardware and firmware ahead of tape-out. You will work closely with RTL design, verification, and firmware teams, learn from senior engineers, and grow into an independent contributor on next-generation semiconductor products. Key Responsibilities Emulation Bring-Up: Support compilation, partitioning, and bring-up of RTL…https://jobseveryhour.com/job/principal-design-verification-engineer-serdes-phy-ip-astera-labs/https://jobseveryhour.com/job/principal-design-verification-engineer-serdes-phy-ip-astera-labs/Tue, 27 Oct 2026 00:00:00 +0000San Jose, California, United States. Astera Labs is hiring a Principal Design Verification Engineer to own functional verification of our high-speed SerDes/PHY IP — the connectivity engine powering rack-scale AI infrastructure. You will architect verification environments, drive coverage closure, and ensure first-pass silicon success on the analog/digital boundary that defines next-generation AI systems. This is a high-impact, hands-on role at the…https://jobseveryhour.com/job/synthesis-sta-engineer-high-speed-serdes-astera-labs/https://jobseveryhour.com/job/synthesis-sta-engineer-high-speed-serdes-astera-labs/Tue, 27 Oct 2026 00:00:00 +0000San Jose, California, United States. Perform RTL synthesis, driving area, power, and timing optimization for digital controller and DSP blocks within high-speed SerDes PHY designs. Author, develop, and validate SDC constraints from scratch, including clock definitions, generated clocks, multi-frequency/multi-mode constraints, I/O delays, false paths, multicycle paths, and clock-domain crossing exceptions unique to SerDes architectures. Set up and…https://jobseveryhour.com/job/senior-design-verification-engineer-astera-labs/https://jobseveryhour.com/job/senior-design-verification-engineer-astera-labs/Tue, 27 Oct 2026 00:00:00 +0000San Jose, California, United States. As a Senior Design Verification Engineer, you will help define and deliver robust verification for next-generation connectivity silicon that enables rack-scale AI infrastructure. You will partner closely with RTL, architecture, firmware, and post-silicon teams to build verification strategies that prove complex switching behavior across high-bandwidth protocols and demanding system environments. This role offers the…https://jobseveryhour.com/job/principal-verification-engineer-astera-labs/https://jobseveryhour.com/job/principal-verification-engineer-astera-labs/Mon, 26 Oct 2026 00:00:00 +0000San Jose, California, United States. Lead the functional verification of advanced ASICs, including test planning, development, execution, and coverage analysis. Collaborate closely with software and system validation teams to create and execute test plans on emulation platforms. Apply both directed and constrained-random verification techniques using SystemVerilog/UVM and other relevant tools. Debug test failures, analyze coverage results, and close…https://jobseveryhour.com/job/staff-engineer-rtl-design-ai-hardware-tenstorrent/https://jobseveryhour.com/job/staff-engineer-rtl-design-ai-hardware-tenstorrent/Mon, 26 Oct 2026 00:00:00 +0000Belgrade, Serbia. to work on challenging, high-impact designs in a fast-paced environment. This role is hybrid, based out of Belgrade, Serbia. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are An engineer with a demonstrated depth in…https://jobseveryhour.com/job/senior-engineer-rtl-design-ai-hardware-tenstorrent/https://jobseveryhour.com/job/senior-engineer-rtl-design-ai-hardware-tenstorrent/Mon, 26 Oct 2026 00:00:00 +0000Belgrade, Serbia. to work on challenging, high-impact designs in a fast-paced environment. This role is hybrid, based out of Belgrade, Serbia. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are An engineer with a strong foundation in…https://jobseveryhour.com/job/director-silicon-logical-design-graphcore/https://jobseveryhour.com/job/director-silicon-logical-design-graphcore/Mon, 26 Oct 2026 00:00:00 +0000Bengaluru, India. Our team is at the forefront of the artificial intelligence revolution, enabling innovators from all industries and sectors to expand human potential with technology. The availability of specialised artificial intelligence compute will be a decisive factor in AI’s rate of progress. Graphcore allows innovators to go further, faster. What we do really makes a difference. We are looking for an experienced engineering…https://jobseveryhour.com/job/sr-fpga-design-engineer-reliable-robotics/https://jobseveryhour.com/job/sr-fpga-design-engineer-reliable-robotics/Thu, 22 Oct 2026 00:00:00 +0000Mountain View, CA. In your role as a FPGA Design Engineer, you will work in a highly collaborative and cross-functional development environment including mutual peer review to maintain high product quality. This work will include FPGA requirements, design, and simulation as well as code synthesis, hardware integration, and testing. You will contribute to multiple FPGA projects in support of the long-term Reliable Robotics technology…https://jobseveryhour.com/job/principal-physical-design-engineer-astera-labs-2/https://jobseveryhour.com/job/principal-physical-design-engineer-astera-labs-2/Thu, 22 Oct 2026 00:00:00 +0000Bengaluru, Karnataka, India. Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software…https://jobseveryhour.com/job/senior-digital-asic-design-engineer-dsp-analog-serdes-celero-communications-inc-3/https://jobseveryhour.com/job/senior-digital-asic-design-engineer-dsp-analog-serdes-celero-communications-inc-3/Wed, 21 Oct 2026 00:00:00 +0000Ottawa, Ontario, Canada. Design and implement high-performance digital circuits and ASIC blocks using Verilog and SystemVerilog. • Develop and integrate DSP, digital communication, and high-speed SerDes functionality into complex ASIC designs. • Work closely with Analog, SerDes, DSP, Architecture, Verification, Physical Design, and Systems teams to develop and integrate mixed-signal ASICs. • Participate in the design and development of…https://jobseveryhour.com/job/senior-digital-asic-design-engineer-dsp-analog-serdes-celero-communications-inc-2/https://jobseveryhour.com/job/senior-digital-asic-design-engineer-dsp-analog-serdes-celero-communications-inc-2/Wed, 21 Oct 2026 00:00:00 +0000Irvine, CA. Design and implement high-performance digital circuits and ASIC blocks using Verilog and SystemVerilog. • Develop and integrate DSP, digital communication, and high-speed SerDes functionality into complex ASIC designs. • Work closely with Analog, SerDes, DSP, Architecture, Verification, Physical Design, and Systems teams to develop and integrate mixed-signal ASICs. • Participate in the design and development of…https://jobseveryhour.com/job/senior-digital-asic-design-engineer-dsp-analog-serdes-celero-communications-inc/https://jobseveryhour.com/job/senior-digital-asic-design-engineer-dsp-analog-serdes-celero-communications-inc/Wed, 21 Oct 2026 00:00:00 +0000San Jose, CA. Design and implement high-performance digital circuits and ASIC blocks using Verilog and SystemVerilog. • Develop and integrate DSP, digital communication, and high-speed SerDes functionality into complex ASIC designs. • Work closely with Analog, SerDes, DSP, Architecture, Verification, Physical Design, and Systems teams to develop and integrate mixed-signal ASICs. • Participate in the design and development of…https://jobseveryhour.com/job/staff-ml-accelerator-architect-waymo/https://jobseveryhour.com/job/staff-ml-accelerator-architect-waymo/Mon, 19 Oct 2026 00:00:00 +0000Mountain View, CA, USA; New York, New York, USA. , you will report to a Hardware Engineering Manager. You will: Analyze inference workloads and map them efficiently to hardware, proposing novel HW-friendly implementations and projecting performance Build scalable tools for performance modeling and evaluation of inference workloads Work closely with compiler and model developers to influence engineering tradeoffs and future model architectures Architect, simulate…https://jobseveryhour.com/job/fpga-engineer-starshield-spacex/https://jobseveryhour.com/job/fpga-engineer-starshield-spacex/Wed, 14 Oct 2026 00:00:00 +0000Hawthorne, CA. Deliver highly reliable firmware for SpaceX-designed hardware Work with engineers across the department to develop new products, from prototype through production and flight Take ownership of your firmware products, including verification testing and writing documentation Follow the SpaceX flight software development process and write great firmware for spaceflight Work in close collaboration with avionics…https://jobseveryhour.com/job/soc-engineer-openai/https://jobseveryhour.com/job/soc-engineer-openai/Wed, 14 Oct 2026 00:00:00 +0000San Francisco. We’re looking for a SoC Engineer to help architect, design, and integrate OpenAI’s first-party AI accelerators. You will build the processor, interconnect, I/O, and platform infrastructure that connects our accelerator designs into complete, functional systems. This role combines architectural judgment with hands-on implementation. You’ll work closely with design, architecture, verification, and software teams…https://jobseveryhour.com/job/tech-lead-analog-mixed-signal-ic-layout-engineer-astera-labs/https://jobseveryhour.com/job/tech-lead-analog-mixed-signal-ic-layout-engineer-astera-labs/Tue, 13 Oct 2026 00:00:00 +0000Singapore, Singapore. Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software…https://jobseveryhour.com/job/senior-analog-mixed-signal-ic-layout-engineer-astera-labs/https://jobseveryhour.com/job/senior-analog-mixed-signal-ic-layout-engineer-astera-labs/Tue, 13 Oct 2026 00:00:00 +0000Singapore, Singapore. Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software…https://jobseveryhour.com/job/principal-physical-design-engineer-astera-labs-4/https://jobseveryhour.com/job/principal-physical-design-engineer-astera-labs-4/Mon, 12 Oct 2026 00:00:00 +0000Ahmedabad, Gujarat, India. Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software…https://jobseveryhour.com/job/sr-asic-design-engineer-silicon-engineering-spacex/https://jobseveryhour.com/job/sr-asic-design-engineer-silicon-engineering-spacex/Fri, 09 Oct 2026 00:00:00 +0000Palo Alto, CA. , you will be developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network. RESPONSIBILITIES: Evaluate architectural trade-offs…https://jobseveryhour.com/job/asic-design-engineer-silicon-engineering-spacex/https://jobseveryhour.com/job/asic-design-engineer-silicon-engineering-spacex/Fri, 09 Oct 2026 00:00:00 +0000Palo Alto, CA. , you will be developing cutting-edge next-generation FPGAs and ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network. RESPONSIBILITIES: Design ASICs and/or…https://jobseveryhour.com/job/digital-asic-design-engineer-attotude/https://jobseveryhour.com/job/digital-asic-design-engineer-attotude/Wed, 07 Oct 2026 00:00:00 +0000Nuremberg, Germany. We are seeking an experienced Digital IC Design Engineer to join our growing team. In this role, you will be part of an experienced design team developing cutting-edge DSP and mixed-signal ICs. This is a hands-on technical position that requires in-depth technical expertise, and the ability to work in a team of highly experienced engineers to accomplish the goals. Key Responsibilities Flow system level requirements…https://jobseveryhour.com/job/fpga-engineer-ew-anduril-industries/https://jobseveryhour.com/job/fpga-engineer-ew-anduril-industries/Mon, 05 Oct 2026 00:00:00 +0000Costa Mesa, California, United States. We are looking for an FPGA Engineer to join our rapidly growing team in Costa Mesa, CA. In this role, you will be responsible for the end-to-end design and verification of projects on the latest AMD/Xilinx SOC/FPGA platforms and helping to establish robust design processes. This will require expertise in HDL languages, FPGA architecture, and AMD/Xilinx development workflow. If you are someone who is ready to own and…https://jobseveryhour.com/job/formal-verification-engineer-tenstorrent/https://jobseveryhour.com/job/formal-verification-engineer-tenstorrent/Mon, 05 Oct 2026 00:00:00 +0000Santa Clara, California, United States; Spain. Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for…https://jobseveryhour.com/job/sr-rf-silicon-software-engineer-rfic-engineering-spacex/https://jobseveryhour.com/job/sr-rf-silicon-software-engineer-rfic-engineering-spacex/Thu, 01 Oct 2026 00:00:00 +0000Redmond, WA. Bring up new RF silicon as the first engineer to power up chips for the very first time Design and build modular, reusable production-ready software driver libraries for low-level silicon control with special attention to timing, throughput, performance, and simplicity Design and build hardware test platforms (hardware-in-the-loop/HTIL/HIL), create automated integration and regression tests, and validate silicon…https://jobseveryhour.com/job/sr-asic-design-engineer-silicon-engineering-spacex-2/https://jobseveryhour.com/job/sr-asic-design-engineer-silicon-engineering-spacex-2/Wed, 30 Sep 2026 00:00:00 +0000Austin, TX. , you will be developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network. RESPONSIBILITIES: Evaluate architectural trade-offs…https://jobseveryhour.com/job/sr-asic-design-engineer-silicon-engineering-spacex-3/https://jobseveryhour.com/job/sr-asic-design-engineer-silicon-engineering-spacex-3/Wed, 30 Sep 2026 00:00:00 +0000Redmond, WA. , you will be developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network. RESPONSIBILITIES: Evaluate architectural trade-offs…https://jobseveryhour.com/job/sr-asic-design-engineer-silicon-engineering-spacex-4/https://jobseveryhour.com/job/sr-asic-design-engineer-silicon-engineering-spacex-4/Wed, 30 Sep 2026 00:00:00 +0000Irvine, CA. , you will be developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network. RESPONSIBILITIES: Evaluate architectural trade-offs…https://jobseveryhour.com/job/fpga-asic-design-engineer-silicon-engineering-spacex-2/https://jobseveryhour.com/job/fpga-asic-design-engineer-silicon-engineering-spacex-2/Wed, 30 Sep 2026 00:00:00 +0000Irvine, CA. , you will be developing cutting-edge next-generation FPGAs and ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network. RESPONSIBILITIES: Design ASICs and/or…https://jobseveryhour.com/job/fpga-asic-design-engineer-silicon-engineering-spacex/https://jobseveryhour.com/job/fpga-asic-design-engineer-silicon-engineering-spacex/Wed, 30 Sep 2026 00:00:00 +0000Redmond, WA. , you will be developing cutting-edge next-generation FPGAs and ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network. RESPONSIBILITIES: Design ASICs and/or…https://jobseveryhour.com/job/rf-silicon-software-engineer-rfic-engineering-spacex/https://jobseveryhour.com/job/rf-silicon-software-engineer-rfic-engineering-spacex/Wed, 30 Sep 2026 00:00:00 +0000Redmond, WA. Bring up new RF silicon as the first engineer to power up chips for the very first time Design and build modular, reusable production-ready software driver libraries for low-level silicon control with special attention to timing, throughput, performance, and simplicity Design and build hardware test platforms (hardware-in-the-loop/HTIL/HIL), create automated integration and regression tests, and validate silicon…https://jobseveryhour.com/job/silicon-emulation-engineer-waymo-2/https://jobseveryhour.com/job/silicon-emulation-engineer-waymo-2/Wed, 30 Sep 2026 00:00:00 +0000Taipei, Taiwan; Hsinchu, Taiwan. Waymo is an autonomous driving technology company with the mission to be the world's most trusted driver. Since its start as the Google Self-Driving Car Project in 2009, Waymo has focused on building the Waymo Driver—The World's Most Experienced Driver™—to improve access to mobility while saving thousands of lives now lost to traffic crashes. The Waymo Driver powers Waymo’s fully autonomous ride-hail service and can…https://jobseveryhour.com/job/principal-verification-engineer-astera-labs-2/https://jobseveryhour.com/job/principal-verification-engineer-astera-labs-2/Tue, 29 Sep 2026 00:00:00 +0000San Jose, California, United States. Lead the functional verification of advanced ASICs, including test planning, development, execution, and coverage analysis. Collaborate closely with software and system validation teams to create and execute test plans on emulation platforms. Apply both directed and constrained-random verification techniques using SystemVerilog/UVM and other relevant tools. Debug test failures, analyze coverage results, and close…https://jobseveryhour.com/job/design-verification-emulation-hardware-river-ai-inc/https://jobseveryhour.com/job/design-verification-emulation-hardware-river-ai-inc/Mon, 28 Sep 2026 00:00:00 +0000Austin, TX, Palo Alto, CA. We are seeking an emulation-focused design verification engineer to drive IP and SoC verification on emulation platforms. Working with simulation-based DV teams, you will translate architectural and microarchitectural definitions into workloads suited to emulation, then adapt and run those tests. You will partner with DV block owners on debug and emulation-specific closure, providing emulation signoff as an input to…https://jobseveryhour.com/job/senior-design-verification-engineer-astera-labs-3/https://jobseveryhour.com/job/senior-design-verification-engineer-astera-labs-3/Mon, 28 Sep 2026 00:00:00 +0000San Jose, California, United States. As a Senior Design Verification Engineer, you will help define and deliver robust verification for next-generation connectivity silicon that enables rack-scale AI infrastructure. You will partner closely with RTL, architecture, firmware, and post-silicon teams to build verification strategies that prove complex switching behavior across high-bandwidth protocols and demanding system environments. This role offers the…https://jobseveryhour.com/job/tech-lead-engineer-design-verification-astera-labs/https://jobseveryhour.com/job/tech-lead-engineer-design-verification-astera-labs/Mon, 28 Sep 2026 00:00:00 +0000San Jose, California, United States. As a Tech Lead Engineer, Design Verification, you will define and deliver robust verification for next-generation connectivity silicon that enables rack-scale AI infrastructure. You will partner closely with RTL, architecture, firmware, and post-silicon teams to build verification strategies that prove complex switching behavior across high-bandwidth protocols and demanding system environments. Within CCE2, you will…https://jobseveryhour.com/job/senior-rtl-design-engineer-envision-employment-solutions/https://jobseveryhour.com/job/senior-rtl-design-engineer-envision-employment-solutions/Sun, 27 Sep 2026 00:00:00 +0000New Cairo City, Cairo Governorate, Egypt. You'll take a design from architecture to tapeout, defining the microarchitecture, writing the RTL, and making sure it's clean enough for synthesis, timing and test teams to build on. It's hands on design work on complex SoCs, with a real say in how each unit is built. WHAT YOU'LL DO Own feasibility studies and help define system architecture, requirements and external interfaces Develop microarchitecture and logic…https://jobseveryhour.com/job/vlsi-functional-safety-hardware-architect-envision-employment-solutions/https://jobseveryhour.com/job/vlsi-functional-safety-hardware-architect-envision-employment-solutions/Sat, 26 Sep 2026 00:00:00 +0000New Cairo City, Cairo Governorate, Egypt. In automotive silicon, a missed fault isn't a bug report, it's a safety risk. You'll define and build the safety mechanisms inside complex ASICs and SoCs, turning ISO 26262 requirements into RTL that is traceable, verifiable and ready for certification. You'll be the bridge between the functional safety team and the designers who build the chip. WHAT YOU'LL DO Contribute to SoC architecture definition, subsystem…https://jobseveryhour.com/job/fpga-associate-winter-2027-astranis/https://jobseveryhour.com/job/fpga-associate-winter-2027-astranis/Wed, 23 Sep 2026 00:00:00 +0000San Francisco. Astranis builds advanced satellites for high orbits, expanding humanity’s reach into the solar system. Today Astranis satellites provide dedicated, secure networks to highly-sophisticated customers across the globe – large enterprises, sovereign governments, and the US military. With five satellites on orbit and many more set to launch soon, the company is servicing a backlog of more than $1 billion of commercial…https://jobseveryhour.com/job/fpga-associate-summer-2027-astranis/https://jobseveryhour.com/job/fpga-associate-summer-2027-astranis/Wed, 23 Sep 2026 00:00:00 +0000San Francisco. Astranis builds advanced satellites for high orbits, expanding humanity’s reach into the solar system. Today Astranis satellites provide dedicated, secure networks to highly-sophisticated customers across the globe – large enterprises, sovereign governments, and the US military. With five satellites on orbit and many more set to launch soon, the company is servicing a backlog of more than $1 billion of commercial…https://jobseveryhour.com/job/fpga-intern-summer-2027-astranis/https://jobseveryhour.com/job/fpga-intern-summer-2027-astranis/Wed, 23 Sep 2026 00:00:00 +0000San Francisco. Astranis builds advanced satellites for high orbits, expanding humanity’s reach into the solar system. Today Astranis satellites provide dedicated, secure networks to highly-sophisticated customers across the globe – large enterprises, sovereign governments, and the US military. With five satellites on orbit and many more set to launch soon, the company is servicing a backlog of more than $1 billion of commercial…https://jobseveryhour.com/job/fpga-intern-winter-2027-astranis/https://jobseveryhour.com/job/fpga-intern-winter-2027-astranis/Wed, 23 Sep 2026 00:00:00 +0000San Francisco. Astranis builds advanced satellites for high orbits, expanding humanity’s reach into the solar system. Today Astranis satellites provide dedicated, secure networks to highly-sophisticated customers across the globe – large enterprises, sovereign governments, and the US military. With five satellites on orbit and many more set to launch soon, the company is servicing a backlog of more than $1 billion of commercial…https://jobseveryhour.com/job/design-verification-tech-lead-serdes-phy-ip-astera-labs/https://jobseveryhour.com/job/design-verification-tech-lead-serdes-phy-ip-astera-labs/Mon, 21 Sep 2026 00:00:00 +0000San Jose, California, United States. Astera Labs is hiring a Principal Design Verification Engineer to own functional verification of our high-speed SerDes/PHY IP — the connectivity engine powering rack-scale AI infrastructure. You will architect verification environments, drive coverage closure, and ensure first-pass silicon success on the analog/digital boundary that defines next-generation AI systems. This is a high-impact, hands-on role at the…https://jobseveryhour.com/job/dft-engineer-astera-labs-3/https://jobseveryhour.com/job/dft-engineer-astera-labs-3/Mon, 21 Sep 2026 00:00:00 +0000Bengaluru, Karnataka, India. RTL Design & Implementation Own RTL design for assigned blocks from microarchitecture through synthesis sign-off Develop high-quality, synthesizable Verilog/SystemVerilog with strong attention to PPA Drive design reviews, lint, CDC, and timing closure activities to silicon-ready quality Cross-Functional Execution Partner with architecture to translate specifications into implementation-ready microarchitecture…https://jobseveryhour.com/job/principal-logic-design-engineer-ualink-ip-subsystem-astera-labs/https://jobseveryhour.com/job/principal-logic-design-engineer-ualink-ip-subsystem-astera-labs/Thu, 17 Sep 2026 00:00:00 +0000Bengaluru, Karnataka, India. We are looking for a Principal Logic Design Engineer with strong expertise in high-performance interconnect and SoC/IP design to lead RTL and microarchitecture development for UALink-based IP/subsystems . Key Responsibilities Lead architecture and RTL development for UALink IP/subsystems. Translate protocol and system requirements into scalable hardware architecture. Design high-bandwidth, low-latency data paths and…https://jobseveryhour.com/job/lead-logic-design-engineer-astera-labs/https://jobseveryhour.com/job/lead-logic-design-engineer-astera-labs/Thu, 17 Sep 2026 00:00:00 +0000Bengaluru, Karnataka, India. We are seeking a Lead Logic Design Engineer with deep expertise in micro-architecture and RTL design to lead the development of complex IPs/subsystems. The candidate will provide technical ownership across architecture, microarchitecture, RTL implementation, integration, and silicon bring-up. Key Responsibilities Lead RTL/microarchitecture development for complex connectivity IP/subsystems . Translate specifications…https://jobseveryhour.com/job/principal-dft-engineer-celero-communications-inc/https://jobseveryhour.com/job/principal-dft-engineer-celero-communications-inc/Wed, 16 Sep 2026 00:00:00 +0000Irvine, California, United States. Develop and implement DFT architecture for ASIC and SoC designs. Perform scan insertion, scan chain planning, and scan compression implementation. Generate and validate ATPG patterns and analyze fault coverage results. Implement and verify MBIST, and other on-chip test features. Collaborate with RTL, verification, and physical design teams to ensure successful DFT integration. Support JTAG and boundary-scan…https://jobseveryhour.com/job/midcore-design-verification-engineer-tenstorrent/https://jobseveryhour.com/job/midcore-design-verification-engineer-tenstorrent/Wed, 16 Sep 2026 00:00:00 +0000Santa Clara, California, United States; Spain. to own meaningful portions of the verification effort—from developing test plans and architecting test benches to debugging failures and driving issues to closure. This role is remote, based out of North America or Spain. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which…https://jobseveryhour.com/job/front-end-design-verification-engineer-tenstorrent/https://jobseveryhour.com/job/front-end-design-verification-engineer-tenstorrent/Tue, 15 Sep 2026 00:00:00 +0000Santa Clara, California, United States; Spain. Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for…https://jobseveryhour.com/job/principal-rtl-design-engineer-io-memory-systems-sambanova/https://jobseveryhour.com/job/principal-rtl-design-engineer-io-memory-systems-sambanova/Mon, 14 Sep 2026 00:00:00 +0000Austin, Texas, United States; San Jose, California, United States. SambaNova is seeking a Principal Engineer to own the design, integration, and implementation of high-speed IO and memory subsystems within the DataScale® platform. This role is central to delivering reliable, high-performance AI systems at scale. You will drive these subsystems across the full product lifecycle, from architecture exploration and microarchitecture definition through RTL and integration of internal…https://jobseveryhour.com/job/manager-design-verification-astera-labs/https://jobseveryhour.com/job/manager-design-verification-astera-labs/Mon, 14 Sep 2026 00:00:00 +0000Tel Aviv-Yafo, Tel Aviv District, Israel. , you will drive verification strategy and execution for complex SoC and IP designs supporting PCIe, CXL, Ethernet, UALink, and other advanced interconnect technologies. You will partner closely with Architecture, Design, Firmware, Post-Silicon Validation, and Program Management teams to ensure first-pass silicon success while scaling methodologies and processes across a growing organization. Key Responsibilities…https://jobseveryhour.com/job/research-engineer-ai-for-chip-design-openai/https://jobseveryhour.com/job/research-engineer-ai-for-chip-design-openai/Fri, 11 Sep 2026 00:00:00 +0000San Francisco. We’re hiring a Research Engineer to help OpenAI models solve chip-design problems through reinforcement learning, tool use, and evaluation. You’ll own experiments from the initial idea through implementation and analysis. That means building environments and evaluations, running training, investigating failures, and using the results to decide what to try next. You’ll also build the software needed to make those…https://jobseveryhour.com/job/senior-design-verification-engineer-astera-labs-2/https://jobseveryhour.com/job/senior-design-verification-engineer-astera-labs-2/Fri, 11 Sep 2026 00:00:00 +0000Toronto, Ontario, Canada. As a Senior Design Verification Engineer, you will help build and validate complex connectivity silicon that enables the next generation of AI infrastructure. You will develop scalable verification environments, integrate UVM and C/C++ workflows, and partner closely with RTL designers to identify and resolve issues across simulation, co-simulation, and emulation. This is an opportunity to contribute across the…https://jobseveryhour.com/job/senior-digital-design-engineer-astera-labs/https://jobseveryhour.com/job/senior-digital-design-engineer-astera-labs/Thu, 10 Sep 2026 00:00:00 +0000Toronto, Ontario, Canada. As a Senior Digital Design Engineer, you will design and integrate high-performance connectivity silicon for the next generation of AI infrastructure. You will contribute across architecture, micro-architecture, RTL implementation, synthesis, timing closure, and IP integration for PCIe and Ethernet controllers, bridges, switches, and related SerDes interfaces. You will work with cross-functional teams to turn…https://jobseveryhour.com/job/principal-emulation-engineer-astera-labs/https://jobseveryhour.com/job/principal-emulation-engineer-astera-labs/Wed, 09 Sep 2026 00:00:00 +0000San Jose, California, United States. As a Principal Emulation Engineer, you will build and operate emulation environments that let verification teams stress-test complex ASICs before silicon. You’ll partner closely with design, verification, firmware, and systems engineers to model hardware-software interactions, exercise high-speed protocols, and isolate issues across RTL, transactors, test environments, and code. Your hands-on leadership will turn…https://jobseveryhour.com/job/software-engineer-ai-for-chip-design-openai/https://jobseveryhour.com/job/software-engineer-ai-for-chip-design-openai/Tue, 08 Sep 2026 00:00:00 +0000San Francisco. We’re hiring a Software Engineer to build the research infrastructure and tooling that help OpenAI models design silicon. You’ll turn chip-design workflows into reliable environments for reinforcement learning and evaluation, and make it easier for researchers to run experiments and iterate on new ideas. You’ll move between software engineering, tool integration, and open research problems. We value strong coding…https://jobseveryhour.com/job/2027-internship-or-graduate-fpga-engineering-qube-research-technologies-2/https://jobseveryhour.com/job/2027-internship-or-graduate-fpga-engineering-qube-research-technologies-2/Tue, 08 Sep 2026 00:00:00 +0000London, Paris, New York. 2027 – Internship or Graduate, FPGA Engineering Programmes offered: Final-year internship, penultimate-year internship, some permanent opportunities Location: London Programme duration: 3–6 months, or full-time graduate, starting in 2027 Who qualifies: Penultimate or final-year students completing a bachelor’s or master’s degree Qube Research & Technologies (QRT) is a global quantitative and systematic investment…https://jobseveryhour.com/job/fpga-engineer-epirus/https://jobseveryhour.com/job/fpga-engineer-epirus/Fri, 04 Sep 2026 00:00:00 +0000Torrance, California, United States. This is an exciting role in a growing company. The ideal candidate for the position is someone who has experience designing, verifying, and integrating state-of-the-art FPGA systems and embedded processing solutions for RF applications. In this role, you will work closely with a talented, multi-disciplinary engineering team to design and manufacture novel RF systems for a variety of platforms in a rapid development…https://jobseveryhour.com/job/sr-staff-engineer-cpu-front-end-verification-tenstorrent/https://jobseveryhour.com/job/sr-staff-engineer-cpu-front-end-verification-tenstorrent/Fri, 04 Sep 2026 00:00:00 +0000Austin, Texas, United States; Santa Clara, California, United States. Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for…https://jobseveryhour.com/job/senior-digital-design-engineer-air-dominance-and-strike-anduril-industries/https://jobseveryhour.com/job/senior-digital-design-engineer-air-dominance-and-strike-anduril-industries/Wed, 02 Sep 2026 00:00:00 +0000Costa Mesa, California, United States. We are looking for an Senior FPGA Design Engineer to join our team in Costa Mesa, CA. In this role, you will design and integrate RTL for FPGA and SoC platforms used in high-performance embedded systems, avionics, and mission-critical hardware. You will work across the full development cycle, from requirements and microarchitecture through RTL implementation, simulation, synthesis, timing closure, lab bring-up, and…https://jobseveryhour.com/job/senior-fpga-verification-engineer-air-dominance-and-strike-anduril-industries/https://jobseveryhour.com/job/senior-fpga-verification-engineer-air-dominance-and-strike-anduril-industries/Wed, 02 Sep 2026 00:00:00 +0000Costa Mesa, California, United States. We are looking for a Senior FPGA Verification Engineer to join our rapidly growing team in Costa Mesa, CA . You will own verification of FPGA/SoC designs on AMD (Xilinx) platforms for flight-critical avionics, with a focus on UVM-based methodology and coverage-driven verification. This will require expertise in SystemVerilog, object-oriented programming, and UVM. If you are someone who has supported rapid avionics…https://jobseveryhour.com/job/mixed-signal-verification-engineer-arago/https://jobseveryhour.com/job/mixed-signal-verification-engineer-arago/Wed, 02 Sep 2026 00:00:00 +0000Paris Offices. to do their life’s work. WHAT YOU’LL DO As Mixed-Signal Verification Engineer you will own the methodology, planning, and execution of mixed-signal verification for digital-to-analog interfaces on Arago's Systems-on-Chip, working across analog, RTL, architecture, and firmware teams to ensure correct integration and drive verification to sign-off. REQUIRED SKILLS AND EXPERIENCE - Strong hands-on experience in ASIC or…https://jobseveryhour.com/job/staff-silicon-verification-engineer-graphcore/https://jobseveryhour.com/job/staff-silicon-verification-engineer-graphcore/Tue, 01 Sep 2026 00:00:00 +0000Bengaluru, India. Verification planning, specification and closure of functional coverage Providing feedback to architects Test generation and failure diagnosis/triage Contributing to shared verification infrastructure Ensuring good communication between sites Essential skills: • Verification experience in relevant industry • Proven leadership and planning skills • Highly motivated, a self starter, and a team player • Ability to work…https://jobseveryhour.com/job/senior-silicon-verification-engineer-graphcore/https://jobseveryhour.com/job/senior-silicon-verification-engineer-graphcore/Tue, 01 Sep 2026 00:00:00 +0000Bengaluru, India. Verification planning, specification and closure of functional coverage Providing feedback to architects Test generation and failure diagnosis/triage Contributing to shared verification infrastructure Ensuring good communication between sites Essential skills: • Verification experience in relevant industry • Proven leadership and planning skills • Highly motivated, a self starter, and a team player • Ability to work…https://jobseveryhour.com/job/senior-silicon-logical-design-engineer-multiple-vacancies-graphcore/https://jobseveryhour.com/job/senior-silicon-logical-design-engineer-multiple-vacancies-graphcore/Tue, 01 Sep 2026 00:00:00 +0000Bengaluru, India. Working within the logical design team, the silicon logical design engineer is responsible for a wide range of logical design tasks. The team is responsible for delivering the Microarchitecture and RTL design to implement the chip architecture specification for Graphcore Silicon, working closely with other engineers within the Silicon team. The successful candidate will be responsible for helping the team deliver…https://jobseveryhour.com/job/formal-verification-and-rtl-design-software-engineer-astera-labs/https://jobseveryhour.com/job/formal-verification-and-rtl-design-software-engineer-astera-labs/Mon, 31 Aug 2026 00:00:00 +0000San Jose, California, United States. Design, develop, and deploy AI applications using LLMs, agentic frameworks, and related technologies to support RTL, physical and analog design, static/lint checking, and formal verification flows. Build infrastructure to deploy LLM-powered engineering assistants and multi-turn dialogue systems that help designers and verification engineers debug faster and close coverage sooner. Develop agentic AI solutions for…