🇺🇸SystemVerilog jobs in San Francisco Bay Area
69 open roles mentioning SystemVerilog in San Francisco Bay Area as of Nov 15, 2026. Astera Labs, SambaNova, OpenAI, Tenstorrent and Astranis have the most. The median advertised salary is $215K.
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Skills asked for in SystemVerilog roles in San Francisco Bay Area
Job titles in SystemVerilog roles in San Francisco Bay Area
Bars show the share of these 69 roles; one role can count in several rows.
- Principal Design Verifiction EngineerSambaNova · 🇺🇸San Jose, California, United States$180K - $225KLead and abovePythonC++Machine Learning
- FPGA Engineering Intern (Summer 2027)Reliable Robotics · 🇺🇸Mountain View, CA$128KInternPythonC++Verilog
- Staff Engineer, Digital ASIC Design — Storage ControllersSK hynix memory solutions America Inc. · 🇺🇸San Jose—Lead and aboveMachine LearningVerilogStorage systems
- RTL Design Engineer, Networking / NoCOpenAI · 🇺🇸San Francisco$287K - $485KHybridVerilogHigh-performance computingASIC
- Principal Design Verification Engineer (AI Fabric Switches)Astera Labs · 🇺🇸San Jose, California, United States$185K - $240KLead and abovePythonC++AI
- Sr/Staff Digital Design EngineerLightmatter · 🇺🇸Mountain View, CA$164K - $222KLead and abovePythonBashVerilog
- DFT EngineerTenstorrent · 🇺🇸Austin, Texas, United States; Fort Collins, Colorado, Uni…—VerilogHardware interfacesCompilers
- Silicon Design LeadOpenAI · 🇺🇸San Francisco$287K - $485KHybridLead and aboveVerilogThreat modelingFirmware
- Principal PCS/PMA RTL Design EngineerAstera Labs · 🇺🇸San Jose, California, United States$185K - $240KLead and abovePythonVerilogPerl
- Technical Lead Digital Design EngineerAstera Labs · 🇺🇸San Jose, California, United States$160K - $200KLead and abovePythonVerilogTest planning
- Design Verification Engineer, New GradSambaNova · 🇺🇸San Jose, California, United States$120K - $150KJuniorPythonVerilogPerl
- Principal Design Verification Engineer- SerDes/PHY IPAstera Labs · 🇺🇸San Jose, California, United States$207K - $230KLead and abovePythonVerilogPerl
- Synthesis & STA Engineer – High-Speed SerDesAstera Labs · 🇺🇸San Jose, California, United States$160K - $200KPythonVerilogPerl
- Senior Design Verification EngineerAstera Labs · 🇺🇸San Jose, California, United States · +1 more location$148K - $165KSeniorPythonVerilogPerl
- Principal Verification EngineerAstera Labs · 🇺🇸San Jose, California, United States · +1 more location$185K - $230KLead and abovePythonC++Verilog
- Sr. FPGA Design EngineerReliable Robotics · 🇺🇸Mountain View, CA$215K - $300KSeniorAgileVerilogFirmware
- Senior Digital ASIC Design Engineer - DSP/Analog/SerDesCelero Communications, Inc. · 🇺🇸San Jose, CA$150K - $250KSeniorPythonMATLABVerilog
- Staff ML Accelerator ArchitectWaymo · 🇺🇸Mountain View, CA, USA; New York, New York, USA$251K - $310KLead and aboveMachine LearningVerilogCompilers
- SoC EngineerOpenAI · 🇺🇸San Francisco$287K - $485KHybridVerilogFirmwareHardware interfaces
- Sr. ASIC Design Engineer (Silicon Engineering)SpaceX · 🇺🇸Palo Alto, CA$175K - $280KSeniorPythonVerilogFirmware
- ASIC Design Engineer (Silicon Engineering)SpaceX · 🇺🇸Palo Alto, CA$135K - $175KPythonC++Bash
- Formal Verification EngineerTenstorrent · 🇺🇸🇪🇸Santa Clara, California, United States; Spain—PythonC++Verilog
- Design Verification Emulation, HardwareRiver AI Inc. · 🇺🇸Austin, TX, Palo Alto, CA$200K - $420KPythonC++CI/CD
- Tech Lead Engineer, Design VerificationAstera Labs · 🇺🇸San Jose, California, United States$176K - $195KLead and abovePythonVerilogPowerShell
- FPGA Associate (Winter 2027)Astranis · 🇺🇸San Francisco—VerilogFPGARTL design
- FPGA Associate (Summer 2027)Astranis · 🇺🇸San Francisco—VerilogFPGARTL design
- FPGA Intern (Summer 2027)Astranis · 🇺🇸San Francisco—InternVerilogFPGARTL design
- FPGA Intern (Winter 2027)Astranis · 🇺🇸San Francisco—InternVerilogFPGARTL design
- Design Verification Tech Lead- SerDes/PHY IPAstera Labs · 🇺🇸San Jose, California, United States$160K - $200KLead and abovePythonVerilogPerl
- Midcore Design Verification EngineerTenstorrent · 🇺🇸🇪🇸Santa Clara, California, United States; Spain—PythonC++Verilog
- Front End Design Verification EngineerTenstorrent · 🇺🇸🇪🇸Santa Clara, California, United States; Spain—PythonC++Verilog
- Principal RTL Design Engineer, IO & Memory SystemsSambaNova · 🇺🇸Austin, Texas, United States; San Jose, California, Unite…$180K - $255KLead and aboveMachine LearningVerilogFirmware
- Research Engineer, AI for Chip DesignOpenAI · 🇺🇸San Francisco$380K - $500KHybridAIVerilogLLM evaluation
- Principal Emulation EngineerAstera Labs · 🇺🇸San Jose, California, United States$207K - $230KLead and abovePythonVerilogPerl
- Software Engineer, AI for Chip DesignOpenAI · 🇺🇸San Francisco$266K - $468KHybridPythonAIVerilog
- Sr. Staff Engineer, CPU (Front-End) VerificationTenstorrent · 🇺🇸Austin, Texas, United States; Santa Clara, California, Un…—Lead and aboveC++VerilogCompilers
- Formal Verification and RTL Design Software EngineerAstera Labs · 🇺🇸San Jose, California, United States$160K - $200KPythonLLMCI/CD
- Senior RTL Design EngineerSambaNova · 🇺🇸Austin, Texas, United States; San Jose, California, Unite…$120K - $200KSeniorPythonLinuxVerilog
- Principal RTL Design EngineerSambaNova · 🇺🇸Austin, Texas, United States; San Jose, California, Unite…$180K - $255KLead and abovePythonVerilogHardware interfaces
- Director of ASIC Design VerificationSambaNova · 🇺🇸San Jose, California, United States$270K - $340KLead and abovePythonMachine LearningVerilog
- Design Verification EngineerSambaNova · 🇺🇸San Jose, California, United States$120K - $200KPythonMachine LearningVerilog
- Senior Hardware Design EngineerSambaNova · 🇺🇸Austin, Texas, United States; San Jose, California, Unite…$120K - $200KSeniorPythonLinuxVerilog
- FPGA RF Signal Processing EngineerMuon Space · 🇺🇸San Jose, CA$190K - $212KRustPythonC++
- Senior FPGA Engineer, Networking & SecurityMuon Space · 🇺🇸San Jose, CA$213K - $237KSeniorVerilogSecurity clearanceNetwork engineering
- Staff Design Verification EngineerCerebras · 🇺🇸Sunnyvale, CA$225K - $270KLead and abovePython.NETVerilog
- Senior Staff Design Verification EngineerCerebras · 🇺🇸Sunnyvale, CA$250K - $300KLead and abovePython.NETVerilog
- ASIC/SOC DFT Engineer (Silicon Engineering)SpaceX · 🇺🇸Palo Alto, CA$135K - $175KPythonBashVerilog
- Staff SoC Design EngineerWaymo · 🇺🇸Mountain View, CA, USA$251K - $310KLead and abovePythonC++Scala
- Principal DFT Engineer (Silicon Engineering)SpaceX · 🇺🇸Palo Alto, CA$220K - $355KLead and abovePythonVerilogPerl
- Design Verification Engineer (Silicon Engineering)SpaceX · 🇺🇸Palo Alto, CA$135K - $155KPythonMATLABVerilog
Showing the newest 50. See all 69 in search
Who is hiring for SystemVerilog roles in San Francisco Bay Area
What SystemVerilog roles in San Francisco Bay Area pay, by level
| Level in the title | Median advertised salary | Roles counted |
|---|---|---|
| No level in the title | $219K | 22 |
| Lead and above | $218K | 23 |
Medians of the midpoints of advertised yearly US-dollar ranges; a level needs at least 15 such roles. Advertised, not verified pay.
Questions about SystemVerilog jobs in San Francisco Bay Area
- How many SystemVerilog jobs in San Francisco Bay Area are open right now?
- There are 69 open SystemVerilog jobs in San Francisco Bay Area at 16 companies on Jobs Every Hour as of Nov 15, 2026. 4 of them were posted in the last seven days. The list is rebuilt every hour from the employers' own careers pages.
- Which companies have the most SystemVerilog jobs in San Francisco Bay Area?
- Right now the most openings are at Astera Labs (17), SambaNova (8), OpenAI (6), Tenstorrent (6) and Astranis (6). The ranking changes as companies open and close roles.
- Are there remote SystemVerilog jobs in San Francisco Bay Area?
- None of the 69 open SystemVerilog jobs in San Francisco Bay Area are listed as remote at the moment. Remote roles appear here as soon as employers post them.
- What do SystemVerilog jobs in San Francisco Bay Area pay?
- The median advertised salary is $215K, based on 57 open roles that publish a yearly US-dollar range. The middle half of those roles advertise between $180K and $258K. These are advertised ranges, not verified pay. Most employers here are technology companies, so the figures run above the wider market for the same work.
- Is it hard to get one of the SystemVerilog jobs in San Francisco Bay Area?
- 4 of the 69 open SystemVerilog jobs in San Francisco Bay Area (6%) are for beginners: junior roles and internships. Of the 53 postings that state experience, the median asks for 5 years. 16 companies are hiring and 4 roles were posted in the last seven days. Matching your resume to the skills each posting names helps most; the free resume builder shows the match.
- How is AI changing SystemVerilog jobs in San Francisco Bay Area?
- 12 of the 69 open SystemVerilog jobs in San Francisco Bay Area (17%) ask for AI or machine-learning skills, most often Machine Learning, AI, LLM. Employers still list 69 such roles today at 16 companies. Counted from the postings' own text on Nov 15, 2026.
- What skills do SystemVerilog jobs in San Francisco Bay Area ask for?
- Most often Verilog (100%), SystemVerilog (100%), RTL design (86%), Python (72%), ASIC (71%) of the 69 open postings, counted from their own text on Nov 15, 2026.
- Which job titles come up most in SystemVerilog jobs in San Francisco Bay Area?
- Design Verification Engineer (6), RTL Design Engineer (2), Principal Design Verification Engineer (2), Senior Design Verification Engineer (2), Principal Verification Engineer (2): the most common titles among the 69 open roles, without the level and place notes in brackets.
- Are SystemVerilog jobs in San Francisco Bay Area in demand in 2026?
- 69 SystemVerilog jobs in San Francisco Bay Area are open on Jobs Every Hour today at 16 companies, 0.0% of all 148,162 open jobs here; 4 were posted in the last seven days. The median advertised salary is $215K. 0 (0%) can be done remotely.
- How do I apply for SystemVerilog jobs in San Francisco Bay Area?
- Open a job and press “Apply on company site”. You go straight to the employer's own careers page and apply there. Jobs Every Hour needs no account and charges nothing for applying.
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