Principal Logic Design Engineer - UALink IP/Subsystem is open at Astera Labs in Bengaluru, Karnataka, India. Posted on Sep 17, 2026, and still on Astera Labs’s careers page when we last checked, on Nov 14, 2026.
About the role
We are looking for a Principal Logic Design Engineer with strong expertise in high-performance interconnect and SoC/IP design to lead RTL and microarchitecture development for UALink-based IP/subsystems . Key Responsibilities Lead architecture and RTL development for UALink IP/subsystems. Translate protocol and system requirements into scalable hardware architecture. Design high-bandwidth, low-latency data paths and…
The opening lines of the posting. The rest is on Astera Labs’s careers page.
Hiring at Astera Labs
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