https://jobseveryhour.com/skills/uvm/UVM jobs — Jobs Every HourSun, 15 Nov 2026 19:27:33 +0000https://jobseveryhour.com/job/principal-design-verifiction-engineer-sambanova/https://jobseveryhour.com/job/principal-design-verifiction-engineer-sambanova/Fri, 13 Nov 2026 00:00:00 +0000San Jose, California, United States. Define and own the verification execution plan end to end for a major subsystem of the RDU — test plan, testbench architecture, coverage model, formal verification, and sign-off criteria Serve as the technical authority for verification of your subsystem: review and arbitrate testbench design decisions, and lead debug on the hardest failures Verify functional and performance behavior Build the coverage model for…https://jobseveryhour.com/job/senior-fpga-verification-engineer-anduril-industries-3/https://jobseveryhour.com/job/senior-fpga-verification-engineer-anduril-industries-3/Fri, 13 Nov 2026 00:00:00 +0000Waltham, Massachusetts, United States. The Imaging team is seeking a Senior FPGA Verification Engineer to help design a new product lines. In this role, you will work closely with an interdisciplinary technical team to define, complete the design and analysis, build prototypes leading to ground and flight testing, and mature the prototypes into products. WHAT YOU’LL DO Verification environment architecture and design using tools like SystemVerilog or…https://jobseveryhour.com/job/senior-fpga-verification-engineer-anduril-industries/https://jobseveryhour.com/job/senior-fpga-verification-engineer-anduril-industries/Fri, 13 Nov 2026 00:00:00 +0000Goleta, California, United States. The Imaging team is seeking a Senior FPGA Verification Engineer to help design a new product lines. In this role, you will work closely with an interdisciplinary technical team to define, complete the design and analysis, build prototypes leading to ground and flight testing, and mature the prototypes into products. WHAT YOU’LL DO Verification environment architecture and design using tools like SystemVerilog or…https://jobseveryhour.com/job/senior-fpga-verification-engineer-anduril-industries-2/https://jobseveryhour.com/job/senior-fpga-verification-engineer-anduril-industries-2/Fri, 13 Nov 2026 00:00:00 +0000Boulder, Colorado, United States. The Imaging team is seeking a Senior FPGA Verification Engineer to help design a new product lines. In this role, you will work closely with an interdisciplinary technical team to define, complete the design and analysis, build prototypes leading to ground and flight testing, and mature the prototypes into products. WHAT YOU’LL DO Verification environment architecture and design using tools like SystemVerilog or…https://jobseveryhour.com/job/senior-asic-design-verification-engineer-k2-space/https://jobseveryhour.com/job/senior-asic-design-verification-engineer-k2-space/Wed, 11 Nov 2026 00:00:00 +0000United States - Remote. We are seeking a Senior ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ownership, deep technical…https://jobseveryhour.com/job/principal-asic-design-verification-engineer-k2-space/https://jobseveryhour.com/job/principal-asic-design-verification-engineer-k2-space/Wed, 11 Nov 2026 00:00:00 +0000United States - Remote. We are seeking a Principal ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ownership, deep technical…https://jobseveryhour.com/job/senior-hardware-design-engineer-arago/https://jobseveryhour.com/job/senior-hardware-design-engineer-arago/Wed, 11 Nov 2026 00:00:00 +0000Paris Offices. Design and verify custom digital hardware components and architectures that enable high-performance, tightly integrated computation workloads and interface Arago’s custom tensor unit for advanced AI/ML applications. RESPONSIBILITIES - Design, implement, and verify RTL blocks for memory, control, and compute subsystems within Arago’s custom multiphysics computation unit. - Collaborate with Arago’s system software and…https://jobseveryhour.com/job/principal-design-verification-engineer-ai-fabric-switches-astera-labs/https://jobseveryhour.com/job/principal-design-verification-engineer-ai-fabric-switches-astera-labs/Sat, 07 Nov 2026 00:00:00 +0000San Jose, California, United States. Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software…https://jobseveryhour.com/job/validation-and-verification-engineer-aviation-engineering-skyryse/https://jobseveryhour.com/job/validation-and-verification-engineer-aviation-engineering-skyryse/Fri, 06 Nov 2026 00:00:00 +0000El Segundo, CA. , you will be responsible for the verification, validation, and quality assurance of Fly-by-Wire software, Display software, and FPGA firmware. You will create, execute, review tests at the high-level and low-level requirement levels, including FPGA requirements-based verification through simulation and hardware testing. You will also review requirements, design, code, and HDL using checklists. The ideal candidate…https://jobseveryhour.com/job/dft-engineer-tenstorrent-2/https://jobseveryhour.com/job/dft-engineer-tenstorrent-2/Fri, 06 Nov 2026 00:00:00 +0000Austin, Texas, United States; Fort Collins, Colorado, United States; Santa Clara, California, United States. is Design for Test (DFT) for high-performance designs going into industry leading AI/ML architectures. The person coming into this role will be involved in all implementation aspects from RTL to tapeout for various IPs on the chip. High level challenges include reducing test cost while attaining high coverage, and facilitating debug and yield learnings while minimizing design intrusions. The work is done…https://jobseveryhour.com/job/fpga-engineer-tomorrow-io/https://jobseveryhour.com/job/fpga-engineer-tomorrow-io/Fri, 06 Nov 2026 00:00:00 +0000Golden, Colorado, United States. , you will translate high level design requirements into concrete digital logic designs and contribute to the development of our custom electronic hardware. You will join a collaborative, high-performing environment that values technical excellence, shared accountability, and the pursuit of ambitious, mission-driven engineering goals. PLEASE NOTE: This position requires access to technology that is controlled under…https://jobseveryhour.com/job/principal-design-engineer-astera-labs/https://jobseveryhour.com/job/principal-design-engineer-astera-labs/Fri, 06 Nov 2026 00:00:00 +0000San Jose, California, United States. We are looking for Principal Design Engineers with experience developing micro-architecture and implementation of the front-end circuit design, including RTL, synthesis, IP integration, and block-level verification for high performance network controllers. The candidate must have good knowledge of communication/interface protocols such as PCI-Express (Gen-3 and above), Ualink, Esun, Ethernet etc. Basic…https://jobseveryhour.com/job/senior-fpga-engineer-ii-rocket-lab/https://jobseveryhour.com/job/senior-fpga-engineer-ii-rocket-lab/Thu, 05 Nov 2026 00:00:00 +0000Long Beach, CA. to grow alongside the company. Our comprehensive benefits package includes our industry-leading Employee Stock Purchase Program (with a 15% discount on company stock), top-tier medical plans (HMO, PPO, and a zero cost HDHP option with a significant HSA company contribution), dental and vision coverage, paid vacation and sick time, 11 paid holidays, flexible spending and dependent care accounts, paid parental leave…https://jobseveryhour.com/job/principal-pcs-pma-rtl-design-engineer-astera-labs/https://jobseveryhour.com/job/principal-pcs-pma-rtl-design-engineer-astera-labs/Tue, 03 Nov 2026 00:00:00 +0000San Jose, California, United States. PCS/PMA RTL design and implementation Develop synthesizable Verilog/SystemVerilog RTL for PCS and PMA digital blocks supporting Ethernet, PCIe, UCIe, UALink, and related protocols. Implement PCS functions such as line encoding/decoding (64b/66b, 128b/130b, 8b/10b), scrambling/descrambling, block and word alignment, lane deskew and reordering, gearboxes, elastic buffers/FIFOs, and rate adaptation. Implement forward…https://jobseveryhour.com/job/technical-lead-digital-design-engineer-astera-labs/https://jobseveryhour.com/job/technical-lead-digital-design-engineer-astera-labs/Mon, 02 Nov 2026 00:00:00 +0000San Jose, California, United States. Own the RTL implementation of complex digital designs from micro-architecture through sign-off. Collaborate with verification teams to review test plans and debug issues. Support efforts to achieve timing closure and implement Design-for-Test (DFT) features. Scripting and automation for ASIC methodology improvement. Accountable for quality and overall design success with the support of senior engineers. Required…https://jobseveryhour.com/job/senior-design-verification-engineer-ai-hardware-tenstorrent/https://jobseveryhour.com/job/senior-design-verification-engineer-ai-hardware-tenstorrent/Wed, 28 Oct 2026 00:00:00 +0000Belgrade, Serbia. Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for…https://jobseveryhour.com/job/staff-design-verification-engineer-ai-hardware-tenstorrent/https://jobseveryhour.com/job/staff-design-verification-engineer-ai-hardware-tenstorrent/Wed, 28 Oct 2026 00:00:00 +0000Belgrade, Serbia. Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for…https://jobseveryhour.com/job/design-verification-engineer-new-grad-sambanova/https://jobseveryhour.com/job/design-verification-engineer-new-grad-sambanova/Tue, 27 Oct 2026 00:00:00 +0000San Jose, California, United States. As a new grad Design Verification Engineer, you'll write testbenches, tests, checkers, and coverage in SystemVerilog and UVM for RDU features. You'll run regressions, debug simulation failures, and work with RTL designers to find and fix bugs before tape-out. Responsibilities Write and execute verification plans for chip-level control and initialization features Build SystemVerilog and UVM testbench components…https://jobseveryhour.com/job/junior-emulation-engineer-celero-communications-inc/https://jobseveryhour.com/job/junior-emulation-engineer-celero-communications-inc/Tue, 27 Oct 2026 00:00:00 +0000Cordoba, Argentina. , you will help compile, run, and debug RTL on emulation systems, supporting early validation of hardware and firmware ahead of tape-out. You will work closely with RTL design, verification, and firmware teams, learn from senior engineers, and grow into an independent contributor on next-generation semiconductor products. Key Responsibilities Emulation Bring-Up: Support compilation, partitioning, and bring-up of RTL…https://jobseveryhour.com/job/principal-design-verification-engineer-serdes-phy-ip-astera-labs/https://jobseveryhour.com/job/principal-design-verification-engineer-serdes-phy-ip-astera-labs/Tue, 27 Oct 2026 00:00:00 +0000San Jose, California, United States. Astera Labs is hiring a Principal Design Verification Engineer to own functional verification of our high-speed SerDes/PHY IP — the connectivity engine powering rack-scale AI infrastructure. You will architect verification environments, drive coverage closure, and ensure first-pass silicon success on the analog/digital boundary that defines next-generation AI systems. This is a high-impact, hands-on role at the…https://jobseveryhour.com/job/senior-design-verification-engineer-astera-labs/https://jobseveryhour.com/job/senior-design-verification-engineer-astera-labs/Tue, 27 Oct 2026 00:00:00 +0000San Jose, California, United States. As a Senior Design Verification Engineer, you will help define and deliver robust verification for next-generation connectivity silicon that enables rack-scale AI infrastructure. You will partner closely with RTL, architecture, firmware, and post-silicon teams to build verification strategies that prove complex switching behavior across high-bandwidth protocols and demanding system environments. This role offers the…https://jobseveryhour.com/job/principal-verification-engineer-astera-labs/https://jobseveryhour.com/job/principal-verification-engineer-astera-labs/Mon, 26 Oct 2026 00:00:00 +0000San Jose, California, United States. Lead the functional verification of advanced ASICs, including test planning, development, execution, and coverage analysis. Collaborate closely with software and system validation teams to create and execute test plans on emulation platforms. Apply both directed and constrained-random verification techniques using SystemVerilog/UVM and other relevant tools. Debug test failures, analyze coverage results, and close…https://jobseveryhour.com/job/senior-digital-asic-design-engineer-dsp-analog-serdes-celero-communications-inc-3/https://jobseveryhour.com/job/senior-digital-asic-design-engineer-dsp-analog-serdes-celero-communications-inc-3/Wed, 21 Oct 2026 00:00:00 +0000Ottawa, Ontario, Canada. Design and implement high-performance digital circuits and ASIC blocks using Verilog and SystemVerilog. • Develop and integrate DSP, digital communication, and high-speed SerDes functionality into complex ASIC designs. • Work closely with Analog, SerDes, DSP, Architecture, Verification, Physical Design, and Systems teams to develop and integrate mixed-signal ASICs. • Participate in the design and development of…https://jobseveryhour.com/job/senior-digital-asic-design-engineer-dsp-analog-serdes-celero-communications-inc-2/https://jobseveryhour.com/job/senior-digital-asic-design-engineer-dsp-analog-serdes-celero-communications-inc-2/Wed, 21 Oct 2026 00:00:00 +0000Irvine, CA. Design and implement high-performance digital circuits and ASIC blocks using Verilog and SystemVerilog. • Develop and integrate DSP, digital communication, and high-speed SerDes functionality into complex ASIC designs. • Work closely with Analog, SerDes, DSP, Architecture, Verification, Physical Design, and Systems teams to develop and integrate mixed-signal ASICs. • Participate in the design and development of…https://jobseveryhour.com/job/senior-digital-asic-design-engineer-dsp-analog-serdes-celero-communications-inc/https://jobseveryhour.com/job/senior-digital-asic-design-engineer-dsp-analog-serdes-celero-communications-inc/Wed, 21 Oct 2026 00:00:00 +0000San Jose, CA. Design and implement high-performance digital circuits and ASIC blocks using Verilog and SystemVerilog. • Develop and integrate DSP, digital communication, and high-speed SerDes functionality into complex ASIC designs. • Work closely with Analog, SerDes, DSP, Architecture, Verification, Physical Design, and Systems teams to develop and integrate mixed-signal ASICs. • Participate in the design and development of…https://jobseveryhour.com/job/research-engineer-chip-design-rl-anthropic/https://jobseveryhour.com/job/research-engineer-chip-design-rl-anthropic/Wed, 21 Oct 2026 00:00:00 +0000San Francisco, CA. We're hiring for the Code RL team within the RL organization. As a Research Engineer, you'll advance our models' ability to design silicon. Hardware design is difficult and unforgiving – exactly the sort of domain we want Claude to excel at. You'll leverage your chip design expertise and turn it into tasks and signals for models to learn from. Specifically, you will: Invent, design, and implement RL environments and…https://jobseveryhour.com/job/tech-lead-analog-mixed-signal-ic-layout-engineer-astera-labs/https://jobseveryhour.com/job/tech-lead-analog-mixed-signal-ic-layout-engineer-astera-labs/Tue, 13 Oct 2026 00:00:00 +0000Singapore, Singapore. Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software…https://jobseveryhour.com/job/senior-analog-mixed-signal-ic-layout-engineer-astera-labs/https://jobseveryhour.com/job/senior-analog-mixed-signal-ic-layout-engineer-astera-labs/Tue, 13 Oct 2026 00:00:00 +0000Singapore, Singapore. Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software…https://jobseveryhour.com/job/tech-lead-digital-design-engineer-astera-labs/https://jobseveryhour.com/job/tech-lead-digital-design-engineer-astera-labs/Wed, 30 Sep 2026 00:00:00 +0000San Jose, California, United States. Astera Labs is seeking a Tech Lead Engineer to drive front-end digital design for high-performance switch ASICs that enable rack-scale AI infrastructure. In CCE2, you will translate microarchitecture into robust RTL and lead block-level execution across synthesis, timing, verification, DFT, and physical implementation. This is an opportunity to own critical connectivity technology from architecture through GDS while…https://jobseveryhour.com/job/silicon-emulation-engineer-waymo-2/https://jobseveryhour.com/job/silicon-emulation-engineer-waymo-2/Wed, 30 Sep 2026 00:00:00 +0000Taipei, Taiwan; Hsinchu, Taiwan. Waymo is an autonomous driving technology company with the mission to be the world's most trusted driver. Since its start as the Google Self-Driving Car Project in 2009, Waymo has focused on building the Waymo Driver—The World's Most Experienced Driver™—to improve access to mobility while saving thousands of lives now lost to traffic crashes. The Waymo Driver powers Waymo’s fully autonomous ride-hail service and can…https://jobseveryhour.com/job/principal-verification-engineer-astera-labs-2/https://jobseveryhour.com/job/principal-verification-engineer-astera-labs-2/Tue, 29 Sep 2026 00:00:00 +0000San Jose, California, United States. Lead the functional verification of advanced ASICs, including test planning, development, execution, and coverage analysis. Collaborate closely with software and system validation teams to create and execute test plans on emulation platforms. Apply both directed and constrained-random verification techniques using SystemVerilog/UVM and other relevant tools. Debug test failures, analyze coverage results, and close…https://jobseveryhour.com/job/design-verification-emulation-hardware-river-ai-inc/https://jobseveryhour.com/job/design-verification-emulation-hardware-river-ai-inc/Mon, 28 Sep 2026 00:00:00 +0000Austin, TX, Palo Alto, CA. We are seeking an emulation-focused design verification engineer to drive IP and SoC verification on emulation platforms. Working with simulation-based DV teams, you will translate architectural and microarchitectural definitions into workloads suited to emulation, then adapt and run those tests. You will partner with DV block owners on debug and emulation-specific closure, providing emulation signoff as an input to…https://jobseveryhour.com/job/senior-design-verification-engineer-astera-labs-3/https://jobseveryhour.com/job/senior-design-verification-engineer-astera-labs-3/Mon, 28 Sep 2026 00:00:00 +0000San Jose, California, United States. As a Senior Design Verification Engineer, you will help define and deliver robust verification for next-generation connectivity silicon that enables rack-scale AI infrastructure. You will partner closely with RTL, architecture, firmware, and post-silicon teams to build verification strategies that prove complex switching behavior across high-bandwidth protocols and demanding system environments. This role offers the…https://jobseveryhour.com/job/tech-lead-engineer-design-verification-astera-labs/https://jobseveryhour.com/job/tech-lead-engineer-design-verification-astera-labs/Mon, 28 Sep 2026 00:00:00 +0000San Jose, California, United States. As a Tech Lead Engineer, Design Verification, you will define and deliver robust verification for next-generation connectivity silicon that enables rack-scale AI infrastructure. You will partner closely with RTL, architecture, firmware, and post-silicon teams to build verification strategies that prove complex switching behavior across high-bandwidth protocols and demanding system environments. Within CCE2, you will…https://jobseveryhour.com/job/fpga-associate-winter-2027-astranis/https://jobseveryhour.com/job/fpga-associate-winter-2027-astranis/Wed, 23 Sep 2026 00:00:00 +0000San Francisco. Astranis builds advanced satellites for high orbits, expanding humanity’s reach into the solar system. Today Astranis satellites provide dedicated, secure networks to highly-sophisticated customers across the globe – large enterprises, sovereign governments, and the US military. With five satellites on orbit and many more set to launch soon, the company is servicing a backlog of more than $1 billion of commercial…https://jobseveryhour.com/job/fpga-associate-summer-2027-astranis/https://jobseveryhour.com/job/fpga-associate-summer-2027-astranis/Wed, 23 Sep 2026 00:00:00 +0000San Francisco. Astranis builds advanced satellites for high orbits, expanding humanity’s reach into the solar system. Today Astranis satellites provide dedicated, secure networks to highly-sophisticated customers across the globe – large enterprises, sovereign governments, and the US military. With five satellites on orbit and many more set to launch soon, the company is servicing a backlog of more than $1 billion of commercial…https://jobseveryhour.com/job/fpga-intern-summer-2027-astranis/https://jobseveryhour.com/job/fpga-intern-summer-2027-astranis/Wed, 23 Sep 2026 00:00:00 +0000San Francisco. Astranis builds advanced satellites for high orbits, expanding humanity’s reach into the solar system. Today Astranis satellites provide dedicated, secure networks to highly-sophisticated customers across the globe – large enterprises, sovereign governments, and the US military. With five satellites on orbit and many more set to launch soon, the company is servicing a backlog of more than $1 billion of commercial…https://jobseveryhour.com/job/fpga-intern-winter-2027-astranis/https://jobseveryhour.com/job/fpga-intern-winter-2027-astranis/Wed, 23 Sep 2026 00:00:00 +0000San Francisco. Astranis builds advanced satellites for high orbits, expanding humanity’s reach into the solar system. Today Astranis satellites provide dedicated, secure networks to highly-sophisticated customers across the globe – large enterprises, sovereign governments, and the US military. With five satellites on orbit and many more set to launch soon, the company is servicing a backlog of more than $1 billion of commercial…https://jobseveryhour.com/job/design-verification-tech-lead-serdes-phy-ip-astera-labs/https://jobseveryhour.com/job/design-verification-tech-lead-serdes-phy-ip-astera-labs/Mon, 21 Sep 2026 00:00:00 +0000San Jose, California, United States. Astera Labs is hiring a Principal Design Verification Engineer to own functional verification of our high-speed SerDes/PHY IP — the connectivity engine powering rack-scale AI infrastructure. You will architect verification environments, drive coverage closure, and ensure first-pass silicon success on the analog/digital boundary that defines next-generation AI systems. This is a high-impact, hands-on role at the…https://jobseveryhour.com/job/midcore-design-verification-engineer-tenstorrent/https://jobseveryhour.com/job/midcore-design-verification-engineer-tenstorrent/Wed, 16 Sep 2026 00:00:00 +0000Santa Clara, California, United States; Spain. to own meaningful portions of the verification effort—from developing test plans and architecting test benches to debugging failures and driving issues to closure. This role is remote, based out of North America or Spain. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which…https://jobseveryhour.com/job/front-end-design-verification-engineer-tenstorrent/https://jobseveryhour.com/job/front-end-design-verification-engineer-tenstorrent/Tue, 15 Sep 2026 00:00:00 +0000Santa Clara, California, United States; Spain. Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for…https://jobseveryhour.com/job/manager-design-verification-astera-labs/https://jobseveryhour.com/job/manager-design-verification-astera-labs/Mon, 14 Sep 2026 00:00:00 +0000Tel Aviv-Yafo, Tel Aviv District, Israel. , you will drive verification strategy and execution for complex SoC and IP designs supporting PCIe, CXL, Ethernet, UALink, and other advanced interconnect technologies. You will partner closely with Architecture, Design, Firmware, Post-Silicon Validation, and Program Management teams to ensure first-pass silicon success while scaling methodologies and processes across a growing organization. Key Responsibilities…https://jobseveryhour.com/job/senior-design-verification-engineer-astera-labs-2/https://jobseveryhour.com/job/senior-design-verification-engineer-astera-labs-2/Fri, 11 Sep 2026 00:00:00 +0000Toronto, Ontario, Canada. As a Senior Design Verification Engineer, you will help build and validate complex connectivity silicon that enables the next generation of AI infrastructure. You will develop scalable verification environments, integrate UVM and C/C++ workflows, and partner closely with RTL designers to identify and resolve issues across simulation, co-simulation, and emulation. This is an opportunity to contribute across the…https://jobseveryhour.com/job/principal-emulation-engineer-astera-labs/https://jobseveryhour.com/job/principal-emulation-engineer-astera-labs/Wed, 09 Sep 2026 00:00:00 +0000San Jose, California, United States. As a Principal Emulation Engineer, you will build and operate emulation environments that let verification teams stress-test complex ASICs before silicon. You’ll partner closely with design, verification, firmware, and systems engineers to model hardware-software interactions, exercise high-speed protocols, and isolate issues across RTL, transactors, test environments, and code. Your hands-on leadership will turn…https://jobseveryhour.com/job/cpu-core-design-verification-manager-tenstorrent/https://jobseveryhour.com/job/cpu-core-design-verification-manager-tenstorrent/Tue, 08 Sep 2026 00:00:00 +0000Bengaluru, Karnataka, India. Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for…https://jobseveryhour.com/job/fpga-engineer-epirus/https://jobseveryhour.com/job/fpga-engineer-epirus/Fri, 04 Sep 2026 00:00:00 +0000Torrance, California, United States. This is an exciting role in a growing company. The ideal candidate for the position is someone who has experience designing, verifying, and integrating state-of-the-art FPGA systems and embedded processing solutions for RF applications. In this role, you will work closely with a talented, multi-disciplinary engineering team to design and manufacture novel RF systems for a variety of platforms in a rapid development…https://jobseveryhour.com/job/sr-staff-engineer-cpu-front-end-verification-tenstorrent/https://jobseveryhour.com/job/sr-staff-engineer-cpu-front-end-verification-tenstorrent/Fri, 04 Sep 2026 00:00:00 +0000Austin, Texas, United States; Santa Clara, California, United States. Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for…https://jobseveryhour.com/job/senior-fpga-verification-engineer-air-dominance-and-strike-anduril-industries/https://jobseveryhour.com/job/senior-fpga-verification-engineer-air-dominance-and-strike-anduril-industries/Wed, 02 Sep 2026 00:00:00 +0000Costa Mesa, California, United States. We are looking for a Senior FPGA Verification Engineer to join our rapidly growing team in Costa Mesa, CA . You will own verification of FPGA/SoC designs on AMD (Xilinx) platforms for flight-critical avionics, with a focus on UVM-based methodology and coverage-driven verification. This will require expertise in SystemVerilog, object-oriented programming, and UVM. If you are someone who has supported rapid avionics…https://jobseveryhour.com/job/mixed-signal-verification-engineer-arago/https://jobseveryhour.com/job/mixed-signal-verification-engineer-arago/Wed, 02 Sep 2026 00:00:00 +0000Paris Offices. to do their life’s work. WHAT YOU’LL DO As Mixed-Signal Verification Engineer you will own the methodology, planning, and execution of mixed-signal verification for digital-to-analog interfaces on Arago's Systems-on-Chip, working across analog, RTL, architecture, and firmware teams to ensure correct integration and drive verification to sign-off. REQUIRED SKILLS AND EXPERIENCE - Strong hands-on experience in ASIC or…https://jobseveryhour.com/job/staff-silicon-verification-engineer-graphcore/https://jobseveryhour.com/job/staff-silicon-verification-engineer-graphcore/Tue, 01 Sep 2026 00:00:00 +0000Bengaluru, India. Verification planning, specification and closure of functional coverage Providing feedback to architects Test generation and failure diagnosis/triage Contributing to shared verification infrastructure Ensuring good communication between sites Essential skills: • Verification experience in relevant industry • Proven leadership and planning skills • Highly motivated, a self starter, and a team player • Ability to work…https://jobseveryhour.com/job/senior-silicon-verification-engineer-graphcore/https://jobseveryhour.com/job/senior-silicon-verification-engineer-graphcore/Tue, 01 Sep 2026 00:00:00 +0000Bengaluru, India. Verification planning, specification and closure of functional coverage Providing feedback to architects Test generation and failure diagnosis/triage Contributing to shared verification infrastructure Ensuring good communication between sites Essential skills: • Verification experience in relevant industry • Proven leadership and planning skills • Highly motivated, a self starter, and a team player • Ability to work…https://jobseveryhour.com/job/principal-design-verification-engineer-astera-labs/https://jobseveryhour.com/job/principal-design-verification-engineer-astera-labs/Thu, 27 Aug 2026 00:00:00 +0000Bengaluru, Karnataka, India. Develop and execute block-level and system-level verification plans. Write and execute test sequences and collect and close coverage. Collaborate with RTL designers to debug failures and refine verification processes. Utilize coding and protocol expertise to contribute to functional verification. Develop user-controlled random constraints in transaction-based verification methodologies. Write assertions, cover…https://jobseveryhour.com/job/tech-lead-verification-methodology-cad-astera-labs/https://jobseveryhour.com/job/tech-lead-verification-methodology-cad-astera-labs/Thu, 27 Aug 2026 00:00:00 +0000Bengaluru, Karnataka, India. We are looking for a Tech Lead – Verification Methodology/CAD/Automation Engineer to drive verification infrastructure, methodology, automation, and productivity across IP and SoC verification teams. The candidate will build scalable verification frameworks, automate verification workflows, improve regression infrastructure, and partner with design verification teams to establish efficient and reusable…https://jobseveryhour.com/job/senior-fpga-verification-engineer-ionq/https://jobseveryhour.com/job/senior-fpga-verification-engineer-ionq/Thu, 27 Aug 2026 00:00:00 +0000Oxford, England, United Kingdom. , you will be responsible for supporting the FPGA team with verification test benches, contributing to the team’s mission of delivering the best in class control systems. You’ll play an important part in shaping hardware and RTL that support our work in building the world’s most advanced quantum systems. You will collaborate closely with cross-functional partners to ensure our control systems meet the highest…https://jobseveryhour.com/job/ams-verification-engineer-rfic-engineering-spacex/https://jobseveryhour.com/job/ams-verification-engineer-rfic-engineering-spacex/Mon, 24 Aug 2026 00:00:00 +0000Irvine, CA. , you will be developing cutting-edge next-generation RFICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Join us to help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network. RESPONSIBILITIES: Develop and own “analog-on-top” and…https://jobseveryhour.com/job/ams-verification-engineer-rfic-engineering-spacex-2/https://jobseveryhour.com/job/ams-verification-engineer-rfic-engineering-spacex-2/Mon, 24 Aug 2026 00:00:00 +0000Redmond, WA. , you will be developing cutting-edge next-generation RFICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Join us to help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network. RESPONSIBILITIES: Develop and own “analog-on-top” and…https://jobseveryhour.com/job/fpga-verification-engineer-air-dominance-and-strike-anduril-industries/https://jobseveryhour.com/job/fpga-verification-engineer-air-dominance-and-strike-anduril-industries/Wed, 19 Aug 2026 00:00:00 +0000Costa Mesa, California, United States. We are looking for a FPGA Verification Engineer to join our rapidly growing team in Costa Mesa, CA . You will own verification of FPGA/SoC designs on AMD (Xilinx) platforms for flight-critical avionics, with a focus on UVM-based methodology and coverage-driven verification. This will require expertise in SystemVerilog, object-oriented programming, and UVM. If you are someone who has supported rapid avionics…https://jobseveryhour.com/job/director-of-asic-design-verification-sambanova/https://jobseveryhour.com/job/director-of-asic-design-verification-sambanova/Wed, 19 Aug 2026 00:00:00 +0000San Jose, California, United States. SambaNova Systems is looking for a Director of ASIC Design Verification to own end to end verification for the next generation of our RDU chips. This role asks for genuine depth in verification, not just management of it. You'll be the technical authority on methodology as well as the leader of the team. You'll set verification architecture and strategy across the full chip and be accountable for pre-silicon quality…https://jobseveryhour.com/job/design-verification-engineer-sambanova/https://jobseveryhour.com/job/design-verification-engineer-sambanova/Tue, 18 Aug 2026 00:00:00 +0000San Jose, California, United States. SambaNova Systems is looking for a talented and motivated Design Verification Engineer, DFT to help us build state of the art RDU chips for machine learning and artificial intelligence. Responsibilities Develop and execute comprehensive verification plans for complex chip-level control and initialization features Develop SystemVerilog/UVM based verification environments, test sequences, checkers, assertions, and…https://jobseveryhour.com/job/staff-design-verification-engineer-cerebras/https://jobseveryhour.com/job/staff-design-verification-engineer-cerebras/Wed, 12 Aug 2026 00:00:00 +0000Sunnyvale, CA. Work with architects, designers, post silicon and software engineers to ensure a high-quality design that works first silicon. - Develop and implement verification strategies, detailed tests and coverage plans based on micro-architecture. - Create verification methodologies and reusable environments, including components such as stimulus, checkers, assertions, and coverage. - Implement tests, manage regressions…https://jobseveryhour.com/job/senior-staff-design-verification-engineer-cerebras/https://jobseveryhour.com/job/senior-staff-design-verification-engineer-cerebras/Fri, 07 Aug 2026 00:00:00 +0000Sunnyvale, CA. Work with architects, designers, post silicon and software engineers to ensure a high-quality design that works first silicon. - Develop and implement verification strategies, detailed tests and coverage plans based on micro-architecture. - Create verification methodologies and reusable environments, including components such as stimulus, checkers, assertions, and coverage. - Implement tests, manage regressions…https://jobseveryhour.com/job/verification-engineer-onsite-pa-or-ca-6269-itd-tech/https://jobseveryhour.com/job/verification-engineer-onsite-pa-or-ca-6269-itd-tech/Fri, 07 Aug 2026 00:00:00 +0000Allentown, PA or Carlsbad, CA. Develop and maintain UVM-based verification environments for ASIC/SoC designs. Create and execute block- and system-level verification plans. Design verification components, including assertions, agents, traffic generators, and scoreboards. Partner with cross-functional engineering teams to define verification strategies and improve design testability. Debug and resolve complex design and verification issues…https://jobseveryhour.com/job/sr-asic-design-verification-engineer-silicon-engineering-spacex-4/https://jobseveryhour.com/job/sr-asic-design-verification-engineer-silicon-engineering-spacex-4/Tue, 14 Jul 2026 00:00:00 +0000Austin, TX. , you will be developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network. RESPONSIBILITIES: Responsible for digital ASIC…https://jobseveryhour.com/job/sr-asic-design-verification-engineer-silicon-engineering-spacex-3/https://jobseveryhour.com/job/sr-asic-design-verification-engineer-silicon-engineering-spacex-3/Tue, 14 Jul 2026 00:00:00 +0000Irvine, CA. , you will be developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network. RESPONSIBILITIES: Responsible for digital ASIC…https://jobseveryhour.com/job/sr-asic-design-verification-engineer-silicon-engineering-spacex/https://jobseveryhour.com/job/sr-asic-design-verification-engineer-silicon-engineering-spacex/Tue, 14 Jul 2026 00:00:00 +0000Palo Alto, CA. , you will be developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network. RESPONSIBILITIES: Responsible for digital ASIC…https://jobseveryhour.com/job/sr-asic-design-verification-engineer-silicon-engineering-spacex-2/https://jobseveryhour.com/job/sr-asic-design-verification-engineer-silicon-engineering-spacex-2/Tue, 14 Jul 2026 00:00:00 +0000Redmond, WA. , you will be developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network. RESPONSIBILITIES: Responsible for digital ASIC…https://jobseveryhour.com/job/design-verification-engineer-silicon-engineering-spacex/https://jobseveryhour.com/job/design-verification-engineer-silicon-engineering-spacex/Tue, 14 Jul 2026 00:00:00 +0000Redmond, WA. , you will be developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network. RESPONSIBILITIES: Responsible for digital ASIC…https://jobseveryhour.com/job/design-verification-engineer-silicon-engineering-spacex-2/https://jobseveryhour.com/job/design-verification-engineer-silicon-engineering-spacex-2/Tue, 14 Jul 2026 00:00:00 +0000Palo Alto, CA. , you will be developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network. RESPONSIBILITIES: Responsible for digital ASIC…https://jobseveryhour.com/job/design-verification-engineer-silicon-engineering-spacex-3/https://jobseveryhour.com/job/design-verification-engineer-silicon-engineering-spacex-3/Tue, 14 Jul 2026 00:00:00 +0000Irvine, CA. , you will be developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network. RESPONSIBILITIES: Responsible for digital ASIC…https://jobseveryhour.com/job/design-verification-engineer-silicon-engineering-spacex-4/https://jobseveryhour.com/job/design-verification-engineer-silicon-engineering-spacex-4/Tue, 14 Jul 2026 00:00:00 +0000Austin, TX. , you will be developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network. RESPONSIBILITIES: Responsible for digital ASIC…https://jobseveryhour.com/job/silicon-verification-engineer-multiple-levels-graphcore/https://jobseveryhour.com/job/silicon-verification-engineer-multiple-levels-graphcore/Thu, 02 Jul 2026 00:00:00 +0000Bristol, UK; Cambridge, UK; London, UK. Own verification that turns complex silicon architecture into reliable AI compute hardware. As a Silicon Verification Engineer, you will help ensure Graphcore RTL matches the architecture specification. Your work will protect silicon quality before designs move into physical implementation. You will sit where architecture, logical design and verification meet. You will directly influence how issues are found…https://jobseveryhour.com/job/senior-asic-design-verification-engineer-k2-space-2/https://jobseveryhour.com/job/senior-asic-design-verification-engineer-k2-space-2/Tue, 30 Jun 2026 00:00:00 +0000Seattle, WA. We are seeking a Senior ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ownership, deep technical…https://jobseveryhour.com/job/principal-asic-design-verification-engineer-k2-space-2/https://jobseveryhour.com/job/principal-asic-design-verification-engineer-k2-space-2/Tue, 30 Jun 2026 00:00:00 +0000Seattle, WA. We are seeking a Principal ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ownership, deep technical…https://jobseveryhour.com/job/soc-design-verification-director-astera-labs/https://jobseveryhour.com/job/soc-design-verification-director-astera-labs/Wed, 24 Jun 2026 00:00:00 +0000Bengaluru, Karnataka, India. Own and drive the end-to-end SoC verification methodology, ensuring seamless integration of IP-level verification into system-level environments. Lead, mentor, and grow a diverse team of engineers, fostering technical excellence, innovation, and collaboration. Guide verification of complex SoC subsystems including HSIO, peripherals, interconnects, memory controllers, coherency fabrics, and system-level protocols …https://jobseveryhour.com/job/silicon-emulation-engineer-waymo/https://jobseveryhour.com/job/silicon-emulation-engineer-waymo/Mon, 15 Jun 2026 00:00:00 +0000Mountain View, CA, USA; New York, NY, USA. location or, if the role can be performed remote, the specific salary range for your preferred location, during the hiring process. Waymo employees are also eligible to participate in Waymo’s discretionary annual bonus program, equity incentive plan, and generous Company benefits program, subject to eligibility requirements. Salary Range $175,000 — $215,000 USDhttps://jobseveryhour.com/job/asic-design-verification-engineer-waymo/https://jobseveryhour.com/job/asic-design-verification-engineer-waymo/Wed, 10 Jun 2026 00:00:00 +0000Mountain View, CA, USA. location or, if the role can be performed remote, the specific salary range for your preferred location, during the hiring process. Waymo employees are also eligible to participate in Waymo’s discretionary annual bonus program, equity incentive plan, and generous Company benefits program, subject to eligibility requirements. Salary Range $175,000 — $215,000 USDhttps://jobseveryhour.com/job/design-verification-engineer-cerebras/https://jobseveryhour.com/job/design-verification-engineer-cerebras/Thu, 04 Jun 2026 00:00:00 +0000Sunnyvale, CA. Work with architects, designers, post silicon and software engineers to ensure a high-quality design that works for silicon. - Develop and implement verification strategies, detailed tests and coverage plans based on micro-architecture. - Create verification methodologies and reusable environments, including components such as stimulus, checkers, assertions, and coverage. - Implement tests, manage regressions…https://jobseveryhour.com/job/ai-core-dv-engineer-densityai/https://jobseveryhour.com/job/ai-core-dv-engineer-densityai/Tue, 02 Jun 2026 00:00:00 +0000Mountain View, CA; Austin, TX. Own verification of our AI compute core - tensor pipelines, MAC arrays, accumulator logic, and the compute ↔ memory interconnect. Work with chip-design and software teams driving DensityAI's AI accelerator program from first silicon through scale-out. What you'll do Own verification of our AI compute core - tensor pipelines, MAC arrays, accumulator logic, and the compute ↔ memory interconnect Use and develop…https://jobseveryhour.com/job/staff-principal-design-verification-engineer-astera-labs/https://jobseveryhour.com/job/staff-principal-design-verification-engineer-astera-labs/Mon, 01 Jun 2026 00:00:00 +0000Tel Aviv-Yafo, Tel Aviv District, Israel. Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Staff/ Principal Design Verification Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on…https://jobseveryhour.com/job/senior-design-verification-engineer-astera-labs-4/https://jobseveryhour.com/job/senior-design-verification-engineer-astera-labs-4/Mon, 01 Jun 2026 00:00:00 +0000Tel Aviv-Yafo, Tel Aviv District, Israel. Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Senior Design Verification Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful…https://jobseveryhour.com/job/cpu-verification-fellow-risc-v-high-performance-processor-tenstorrent/https://jobseveryhour.com/job/cpu-verification-fellow-risc-v-high-performance-processor-tenstorrent/Thu, 28 May 2026 00:00:00 +0000Austin, Texas, United States; Santa Clara, California, United States. Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for…https://jobseveryhour.com/job/system-ip-rtl-design-lead-tenstorrent/https://jobseveryhour.com/job/system-ip-rtl-design-lead-tenstorrent/Tue, 26 May 2026 00:00:00 +0000Bengaluru, Karnataka, India. Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for…https://jobseveryhour.com/job/sr-staff-engineer-design-verification-system-ip-tenstorrent/https://jobseveryhour.com/job/sr-staff-engineer-design-verification-system-ip-tenstorrent/Mon, 25 May 2026 00:00:00 +0000Bengaluru, Karnataka, India. , you will be responsible for the end-to-end verification of our IOMMU (Input/Output Memory Management Unit) IP. You will play a critical role in ensuring the functional correctness and performance of the design, taking ownership of the verification process right from the initial specification understanding down to final coverage closure. This role is hybrid, based out of Bangalore, India. We welcome candidates at…https://jobseveryhour.com/job/cpu-core-design-verification-testbench-lead-tenstorrent/https://jobseveryhour.com/job/cpu-core-design-verification-testbench-lead-tenstorrent/Fri, 22 May 2026 00:00:00 +0000Austin, Texas, United States; Santa Clara, California, United States. Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for…https://jobseveryhour.com/job/staff-engineer-cpu-core-verification-tenstorrent/https://jobseveryhour.com/job/staff-engineer-cpu-core-verification-tenstorrent/Wed, 20 May 2026 00:00:00 +0000Bengaluru, Karnataka, India. Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for…https://jobseveryhour.com/job/design-verification-engineer-densityai/https://jobseveryhour.com/job/design-verification-engineer-densityai/Tue, 19 May 2026 00:00:00 +0000Mountain View, CA. We're looking for an experienced Design Verification engineer with at least 5 years of pre-silicon verification experience in end to end verification for complex IP, subsystems, and/or SoC system level verification from plan to functional closure. This is a senior individual-contributor role and you'll partner closely with our HW-design and software teams, driving DensityAI's AI accelerator program from first…https://jobseveryhour.com/job/design-verification-engineer-hardware-river-ai-inc/https://jobseveryhour.com/job/design-verification-engineer-hardware-river-ai-inc/Fri, 15 May 2026 00:00:00 +0000Palo Alto, CA; Austin, TX. We are seeking exception design verification engineers to ensure our high-performance custom silicon is functionally correct. Starting from architectural and micro-architectural definitions, you will define test bench boundaries and implement test environments across a variety of verification methodologies (simulation, formal, emulation, etc). You will collaborate with RTL design, performance modeling and…https://jobseveryhour.com/job/senior-fpga-engineer-epirus/https://jobseveryhour.com/job/senior-fpga-engineer-epirus/Thu, 30 Apr 2026 00:00:00 +0000Torrance, California, United States. About Epirus E pirus is a high-growth technology company dedicated to overcoming the asymmetric challenges inherent to the future of national security. Epirus' flagship product, Leonidas, is a software-defined system built using intelligent power management techniques which allow power-hungry systems to do more with less. Job objective: This is an exciting role an innovative, high-growth defense technology company…https://jobseveryhour.com/job/senior-emulation-engineer-encharge-ai/https://jobseveryhour.com/job/senior-emulation-engineer-encharge-ai/Wed, 08 Apr 2026 00:00:00 +0000India. At EnCharge AI, we are building the next generation of AI compute silicon — purpose-built for high-performance, low-power, and scalable AI inference. As an Emulation Engineer, you will play a critical role in validating complex AI accelerator architectures on emulation platforms before tape-out. This position is ideal for someone passionate about bridging the gap between hardware and software in fast-paced, deep…https://jobseveryhour.com/job/senior-staff-formal-verification-engineer-astera-labs/https://jobseveryhour.com/job/senior-staff-formal-verification-engineer-astera-labs/Wed, 18 Mar 2026 00:00:00 +0000Tel Aviv-Yafo, Tel Aviv District, Israel. Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Formal Verification Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product…https://jobseveryhour.com/job/asic-engineer-falcomm/https://jobseveryhour.com/job/asic-engineer-falcomm/Thu, 12 Mar 2026 00:00:00 +0000Atlanta, Georgia, United States. Design and implement digital and/or mixed-signal ASIC blocks from specification to tapeout Develop RTL (Verilog/SystemVerilog) and/or transistor-level designs depending on focus area Collaborate with RFIC, analog, and system engineers to integrate digital logic within RF and mixed-signal chip architectures. Perform synthesis, timing closure, and power optimization Work with verification engineers to define…https://jobseveryhour.com/job/ip-design-verification-director-astera-labs/https://jobseveryhour.com/job/ip-design-verification-director-astera-labs/Thu, 05 Mar 2026 00:00:00 +0000Bengaluru, Karnataka, India. Own and drive the end-to-end verification methodology for a specific product line. Lead, mentor, and grow a team of engineers, fostering technical excellence and innovation. Guide verification of industry-standard protocols such as PCIe and CXL across Physical, Link, and Transaction layers. Champion advanced methodologies (UVM, formal verification, AI-augmented flows) to accelerate coverage closure and improve…https://jobseveryhour.com/job/design-verification-engineer-automotive-robotics-tenstorrent/https://jobseveryhour.com/job/design-verification-engineer-automotive-robotics-tenstorrent/Mon, 02 Mar 2026 00:00:00 +0000Munich, Germany. Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for…https://jobseveryhour.com/job/principal-digital-design-engineer-ai-fabric-astera-labs/https://jobseveryhour.com/job/principal-digital-design-engineer-ai-fabric-astera-labs/Tue, 30 Dec 2025 00:00:00 +0000San Jose, CA. Develop and implement complex digital blocks and subsystems by defining micro-architecture and driving digital design. Collaborate with verification teams to develop test plans, achieve coverage closure, and debug complex issues. Lead efforts to achieve timing closure and implement Design-for-Test (DFT) features for optimal design performance. Work closely with post-silicon teams to facilitate silicon bring-up and…https://jobseveryhour.com/job/director-silicon-verification-graphcore/https://jobseveryhour.com/job/director-silicon-verification-graphcore/Wed, 10 Dec 2025 00:00:00 +0000Bristol, UK. to make an impact on the company, our products and the future of artificial intelligence. The Team The Verification team sits within the Silicon Design organisation. We ensure that the RTL delivered by Logical Design and used by Physical Design team implements Graphcore’s architectural needs and meets the company's quality standards. As a Director of Silicon Verification, you will help lead this multi-site…https://jobseveryhour.com/job/staff-sr-staff-design-verification-lightmatter-2/https://jobseveryhour.com/job/staff-sr-staff-design-verification-lightmatter-2/Tue, 09 Dec 2025 00:00:00 +0000Boston, MA. will include working alongside photonic and analog designers, gaining a deep understanding of their innovative designs, and applying Real Number Modeling (RNM) and AMS verification methods. This critical function ensures the integrity of their work. We are hiring at multiple levels. Your interaction with the Architecture team will be crucial in comprehending system requirements and spearheading performance…https://jobseveryhour.com/job/staff-sr-staff-design-verification-lightmatter/https://jobseveryhour.com/job/staff-sr-staff-design-verification-lightmatter/Tue, 09 Dec 2025 00:00:00 +0000Mountain View, CA. will include working alongside photonic and analog designers, gaining a deep understanding of their innovative designs, and applying Real Number Modeling (RNM) and AMS verification methods. This critical function ensures the integrity of their work. We are hiring at multiple levels. Your interaction with the Architecture team will be crucial in comprehending system requirements and spearheading performance…https://jobseveryhour.com/job/principal-silicon-verification-engineer-graphcore/https://jobseveryhour.com/job/principal-silicon-verification-engineer-graphcore/Thu, 13 Nov 2025 00:00:00 +0000Bengaluru, India. Working within the Silicon verification team, the silicon verification engineer is responsible for a wide range of tasks within the silicon verification team. This person is responsible for verification activities within Graphcore, helping the silicon team meet the company objectives for quality silicon delivery. The Team The verification team sits within the Silicon design team. We are responsible for ensuring that…https://jobseveryhour.com/job/staff-sr-staff-design-verification-engineer-lightmatter/https://jobseveryhour.com/job/staff-sr-staff-design-verification-engineer-lightmatter/Tue, 04 Nov 2025 00:00:00 +0000Toronto, ON. will include working alongside photonic and analog designers, gaining a deep understanding of their innovative designs, and applying Real Number Modeling (RNM) and AMS verification methods. This critical function ensures the integrity of their work. We are hiring at multiple levels. Your interaction with the Architecture team will be crucial in comprehending system requirements and spearheading performance…https://jobseveryhour.com/job/design-verification-engineer-openai/https://jobseveryhour.com/job/design-verification-engineer-openai/Wed, 29 Oct 2025 00:00:00 +0000San Francisco. OpenAI is developing custom silicon to power the next generation of frontier AI models. We’re looking for experienced Design Verification (DV) Engineers to ensure functional correctness and robust design for our cutting-edge ML accelerators. You will play a key role in verifying complex hardware systems—ranging from individual IP blocks to subsystems and full SoC—working closely with architecture, RTL, software, and…