https://jobseveryhour.com/skills/cadence/Cadence jobs — Jobs Every HourSun, 15 Nov 2026 19:27:35 +0000https://jobseveryhour.com/job/business-recruiter-openai/https://jobseveryhour.com/job/business-recruiter-openai/Fri, 13 Nov 2026 00:00:00 +0000Tokyo, Japan. Own end-to-end hiring for roles in Japan, from scoping and calibration through to offer and close. - Partner closely with senior business leaders to deeply understand team needs, define hiring strategies, and translate business priorities into actionable talent plans. - Build and execute proactive, data-informed sourcing strategies to attract high-calibre and diverse talent across competitive markets. - Act as a…https://jobseveryhour.com/job/electrical-engineer-alten-technology-usa-2/https://jobseveryhour.com/job/electrical-engineer-alten-technology-usa-2/Thu, 12 Nov 2026 00:00:00 +0000Greensboro, North Carolina, United States. Provide engineering support to manufacturing operations and contribute to ongoing product enhancements. Analyze, diagnose, and troubleshoot both analog and digital electronic circuits. Develop, review, and carry out engineering test procedures, records, and supporting documentation. Contribute to design reviews with internal engineering teams as well as external suppliers. Assist with verification and validation…https://jobseveryhour.com/job/senior-asic-physical-design-engineer-k2-space-2/https://jobseveryhour.com/job/senior-asic-physical-design-engineer-k2-space-2/Wed, 11 Nov 2026 00:00:00 +0000United States - Remote. We are seeking a Senior ASIC Physical Design Engineer to help implement advanced SoCs that power next-generation satellite and space systems. In this role, you will contribute to the full physical design flow—from synthesis to GDSII—working closely with architecture, RTL, verification, and packaging teams. You’ll be a key contributor in achieving timing closure, optimizing PPA, and supporting design integration with…https://jobseveryhour.com/job/principal-asic-physical-design-engineer-k2-space-2/https://jobseveryhour.com/job/principal-asic-physical-design-engineer-k2-space-2/Wed, 11 Nov 2026 00:00:00 +0000United States - Remote. We are looking for a Principal ASIC Physical Design Engineer to lead the implementation of complex SoCs for next-generation satellite and space systems. You will own the full physical design flow—from RTL handoff to GDSII—and collaborate closely with architecture, RTL design, DFT, and packaging teams. This role also involves managing external physical design partners, driving tool and flow decisions, and ensuring…https://jobseveryhour.com/job/principal-asic-synthesis-and-timing-engineer-k2-space/https://jobseveryhour.com/job/principal-asic-synthesis-and-timing-engineer-k2-space/Wed, 11 Nov 2026 00:00:00 +0000United States - Remote. We are looking for a Principal ASIC Synthesis and Timing Engineer to lead the implementation of complex SoCs for next-generation satellite and space systems. You will own the constraints development and validation—from RTL handoff to synthesis —and collaborate closely with architecture, RTL design, DFT, and physical design team. This role also involves managing external physical design partners, driving convergence…https://jobseveryhour.com/job/sr-physical-design-flow-methodology-engineer-lightmatter/https://jobseveryhour.com/job/sr-physical-design-flow-methodology-engineer-lightmatter/Wed, 11 Nov 2026 00:00:00 +0000Boston, MA. Develop, maintain and extend our physical design flows from synthesis through signoff (place-and-route, CTS, STA, power integrity, DRC/LVS), mostly in Python and TCL. Use AI and LLM-based tools to automate flow tasks such as report triage, debug, constraint checking, DRC/LVS analysis, run monitoring and QoR prediction. Research and prototype new flow capabilities, EDA tool features and methodologies, then turn the…https://jobseveryhour.com/job/associate-medical-writer-allegro-write-at-inizio-medical-inizio-medical-4/https://jobseveryhour.com/job/associate-medical-writer-allegro-write-at-inizio-medical-inizio-medical-4/Wed, 11 Nov 2026 00:00:00 +0000Macclesfield, United Kingdom. you must have a minimum of a 2:1 in a Life Sciences degree. No previous writing experience is necessary, but good written and verbal communication skills, an awareness of the pharmaceutical industry, a keen eye for detail, and a passion for knowledge are important! You must have a full right to work in the UK and be available for training across July and August. What’s the recruitment process? To apply, please send…https://jobseveryhour.com/job/associate-medical-writer-allegro-write-at-inizio-medical-inizio-medical-5/https://jobseveryhour.com/job/associate-medical-writer-allegro-write-at-inizio-medical-inizio-medical-5/Wed, 11 Nov 2026 00:00:00 +0000Manchester, United Kingdom. you must have a minimum of a 2:1 in a Life Sciences degree. No previous writing experience is necessary, but good written and verbal communication skills, an awareness of the pharmaceutical industry, a keen eye for detail, and a passion for knowledge are important! You must have a full right to work in the UK and be available for training across July and August. What’s the recruitment process? To apply, please send…https://jobseveryhour.com/job/staff-engineer-digital-asic-design-storage-controllers-sk-hynix-memory-solutions-america-inc/https://jobseveryhour.com/job/staff-engineer-digital-asic-design-storage-controllers-sk-hynix-memory-solutions-america-inc/Tue, 10 Nov 2026 00:00:00 +0000San Jose. Join our digital ASIC design team to develop IP for next-generation SSD controllers and storage solutions. This role offers opportunities across the controller architecture, including host interfaces, on-chip interconnects, and back-end NAND subsystems. You will translate product requirements into microarchitecture specifications, implement high-quality RTL, and collaborate with verification and physical design…https://jobseveryhour.com/job/sr-staff-digital-design-engineer-lightmatter-3/https://jobseveryhour.com/job/sr-staff-digital-design-engineer-lightmatter-3/Fri, 06 Nov 2026 00:00:00 +0000Toronto, ON. Develop RTL (i.e. system Verilog) modules with DFT considerations for IC development Debug complex logic and mixed signal simulations Understand and integrate silicon photonic communication and compute technology into digital accelerator design Actively work with Architecture, Design Verification, Physical Design, Photonic, Analog and Software teams to realize high performance, low power designs in advanced…https://jobseveryhour.com/job/sr-staff-digital-design-engineer-lightmatter-2/https://jobseveryhour.com/job/sr-staff-digital-design-engineer-lightmatter-2/Fri, 06 Nov 2026 00:00:00 +0000Boston, MA. Develop RTL (i.e. system Verilog) modules with DFT considerations for IC development Debug complex logic and mixed signal simulations Understand and integrate silicon photonic communication and compute technology into digital accelerator design Actively work with Architecture, Design Verification, Physical Design, Photonic, Analog and Software teams to realize high performance, low power designs in advanced…https://jobseveryhour.com/job/sr-staff-digital-design-engineer-lightmatter/https://jobseveryhour.com/job/sr-staff-digital-design-engineer-lightmatter/Fri, 06 Nov 2026 00:00:00 +0000Mountain View, CA. Develop RTL (i.e. system Verilog) modules with DFT considerations for IC development Debug complex logic and mixed signal simulations Understand and integrate silicon photonic communication and compute technology into digital accelerator design Actively work with Architecture, Design Verification, Physical Design, Photonic, Analog and Software teams to realize high performance, low power designs in advanced…https://jobseveryhour.com/job/physical-design-and-cad-engineer-astera-labs/https://jobseveryhour.com/job/physical-design-and-cad-engineer-astera-labs/Fri, 06 Nov 2026 00:00:00 +0000San Jose, California, United States. As a Physical Design & CAD Engineer , you will serve as a Technical Lead developing Astera Labs’ next-generation connectivity ASICs for cloud and AI infrastructure. This role combines Physical Design CAD methodology development with hands-on place-and-route (PNR) implementation. You will develop and optimize automated design flows for advanced process nodes while contributing to block-level physical design, timing…https://jobseveryhour.com/job/dft-engineer-tenstorrent-2/https://jobseveryhour.com/job/dft-engineer-tenstorrent-2/Fri, 06 Nov 2026 00:00:00 +0000Austin, Texas, United States; Fort Collins, Colorado, United States; Santa Clara, California, United States. is Design for Test (DFT) for high-performance designs going into industry leading AI/ML architectures. The person coming into this role will be involved in all implementation aspects from RTL to tapeout for various IPs on the chip. High level challenges include reducing test cost while attaining high coverage, and facilitating debug and yield learnings while minimizing design intrusions. The work is done…https://jobseveryhour.com/job/principal-design-engineer-astera-labs/https://jobseveryhour.com/job/principal-design-engineer-astera-labs/Fri, 06 Nov 2026 00:00:00 +0000San Jose, California, United States. We are looking for Principal Design Engineers with experience developing micro-architecture and implementation of the front-end circuit design, including RTL, synthesis, IP integration, and block-level verification for high performance network controllers. The candidate must have good knowledge of communication/interface protocols such as PCI-Express (Gen-3 and above), Ualink, Esun, Ethernet etc. Basic…https://jobseveryhour.com/job/mixed-signal-ic-design-engineer-arago/https://jobseveryhour.com/job/mixed-signal-ic-design-engineer-arago/Wed, 04 Nov 2026 00:00:00 +0000Paris Offices. Design, integrate, and deliver high-performance digital subsystems within mixed-signal ICs, enabling control, calibration, and high-speed data movement in analog-centric environments — owning the flow from RTL to physical implementation and tape-out. RESPONSIBILITIES - Design and verify digital subsystems that interface directly with high-speed analog and mixed-signal circuits — including calibration engines…https://jobseveryhour.com/job/principal-pcs-pma-rtl-design-engineer-astera-labs/https://jobseveryhour.com/job/principal-pcs-pma-rtl-design-engineer-astera-labs/Tue, 03 Nov 2026 00:00:00 +0000San Jose, California, United States. PCS/PMA RTL design and implementation Develop synthesizable Verilog/SystemVerilog RTL for PCS and PMA digital blocks supporting Ethernet, PCIe, UCIe, UALink, and related protocols. Implement PCS functions such as line encoding/decoding (64b/66b, 128b/130b, 8b/10b), scrambling/descrambling, block and word alignment, lane deskew and reordering, gearboxes, elastic buffers/FIFOs, and rate adaptation. Implement forward…https://jobseveryhour.com/job/technical-lead-digital-design-engineer-astera-labs/https://jobseveryhour.com/job/technical-lead-digital-design-engineer-astera-labs/Mon, 02 Nov 2026 00:00:00 +0000San Jose, California, United States. Own the RTL implementation of complex digital designs from micro-architecture through sign-off. Collaborate with verification teams to review test plans and debug issues. Support efforts to achieve timing closure and implement Design-for-Test (DFT) features. Scripting and automation for ASIC methodology improvement. Accountable for quality and overall design success with the support of senior engineers. Required…https://jobseveryhour.com/job/principal-physical-design-cad-engineer-astera-labs/https://jobseveryhour.com/job/principal-physical-design-cad-engineer-astera-labs/Sun, 01 Nov 2026 00:00:00 +0000Tel Aviv-Yafo, Tel Aviv District, Israel. Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, We are looking for a Physical Design CAD Engineer with at least 3 years of hands-on experience in digital implementation flows. The ideal candidate is highly technical, curious, and…https://jobseveryhour.com/job/staff-principal-physical-design-sta-engineer-astera-labs-2/https://jobseveryhour.com/job/staff-principal-physical-design-sta-engineer-astera-labs-2/Sun, 01 Nov 2026 00:00:00 +0000Haifa District, Israel. Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Static Timing Analysis (STA) Engineer to join our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful…https://jobseveryhour.com/job/dft-engineer-astera-labs/https://jobseveryhour.com/job/dft-engineer-astera-labs/Sun, 01 Nov 2026 00:00:00 +0000Haifa District, Israel. Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary DFT Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new…https://jobseveryhour.com/job/staff-dft-engineer-astera-labs/https://jobseveryhour.com/job/staff-dft-engineer-astera-labs/Sun, 01 Nov 2026 00:00:00 +0000Haifa District, Israel. Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Staff DFT Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a…https://jobseveryhour.com/job/principal-dft-engineer-astera-labs-3/https://jobseveryhour.com/job/principal-dft-engineer-astera-labs-3/Sun, 01 Nov 2026 00:00:00 +0000Haifa District, Israel. Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Principal DFT Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership…https://jobseveryhour.com/job/senior-staff-physical-design-engineer-astera-labs-2/https://jobseveryhour.com/job/senior-staff-physical-design-engineer-astera-labs-2/Sun, 01 Nov 2026 00:00:00 +0000Tel Aviv-Yafo, Tel Aviv District, Israel. Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Physical Design Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership…https://jobseveryhour.com/job/physical-design-team-lead-astera-labs-2/https://jobseveryhour.com/job/physical-design-team-lead-astera-labs-2/Sun, 01 Nov 2026 00:00:00 +0000Haifa District, Israel. Astera Labs is a hyper-growth connectivity company building the purpose-built silicon that powers rack-scale AI infrastructure. As a Principal Physical Design Engineer and Team Lead in Israel, you will lead physical design teams that take complex, high-speed mixed-signal and digital SoCs from RTL handoff through tapeout. You will set the technical direction, drive execution across multiple projects, and grow the…https://jobseveryhour.com/job/staff-principal-chip-top-physical-design-engineer-astera-labs-2/https://jobseveryhour.com/job/staff-principal-chip-top-physical-design-engineer-astera-labs-2/Sun, 01 Nov 2026 00:00:00 +0000Haifa District, Israel. Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Chip Top Physical Design Engineer focusing on implementation to join our local engineering powerhouse from the ground up. If you thrive on solving complex…https://jobseveryhour.com/job/eda-tools-design-automation-engineer-tenstorrent/https://jobseveryhour.com/job/eda-tools-design-automation-engineer-tenstorrent/Fri, 30 Oct 2026 00:00:00 +0000Santa Clara, California, United States. , you will own the deployment, configuration, reliability, and ongoing evolution of the EDA tool environment used by our mixed-signal design teams. You will develop and maintain AI-enabled design-automation tooling; build automation using Python and EDA-specific scripting languages; partner with CAD on tool and PDK configuration; and help define and support scalable EDA flows that enable faster, more reliable…https://jobseveryhour.com/job/senior-staff-pcb-layout-engineer-skydio/https://jobseveryhour.com/job/senior-staff-pcb-layout-engineer-skydio/Thu, 29 Oct 2026 00:00:00 +0000US Remote. At Skydio, we’re building the world’s most intelligent autonomous drones. We’re looking for a PCB Layout Engineer who can execute on complex layouts, while also working cross functionally with EE, RF, and Mechanical. You’ll set best practices, own challenging boards, and play a key role in ensuring Skydio’s layouts meet world-class performance, reliability, and manufacturability standards. How you'll make an impact…https://jobseveryhour.com/job/soc-clocking-specialist-physical-design-encharge-ai/https://jobseveryhour.com/job/soc-clocking-specialist-physical-design-encharge-ai/Wed, 28 Oct 2026 00:00:00 +0000India. We are looking for a highly skilled SoC Clocking Specialist to lead the clock architecture and physical implementation of our next-generation edge AI hardware. In this critical role, you will bridge the gap between frontend logic and backend execution, partnering directly with Architecture, RTL, and Timing teams to architect, implement, and sign-off a highly robust and power-efficient clock tree on advanced…https://jobseveryhour.com/job/eda-and-cad-lead-engineer-manager-attotude/https://jobseveryhour.com/job/eda-and-cad-lead-engineer-manager-attotude/Wed, 28 Oct 2026 00:00:00 +0000Menlo Park, CA, Bethlehem, PA. , you will be part of the experience design and layout team to develop cutting-edge mixed-signal ICs. You will be involved in the technical aspects of the ASIC design and development, from concept through to production. This is a hands-on technical position that requires in-depth technical expertise, and the ability to work in a team of highly experienced engineers to accomplish the goals. Key Responsibilities…https://jobseveryhour.com/job/physical-design-engineer-new-grad-sambanova/https://jobseveryhour.com/job/physical-design-engineer-new-grad-sambanova/Tue, 27 Oct 2026 00:00:00 +0000San Jose, California, United States. As a new grad Physical Design Engineer, you'll run and improve our RTL to GDS flow on advanced process nodes. You'll write TCL and Python scripts to automate flow steps, help physical designers debug timing and congestion issues, and work with tool vendors on bugs. Responsibilities Run synthesis and place and route using Cadence Genus, Innovus, and Cerebrus Write scripts in TCL and Python to automate and improve the…https://jobseveryhour.com/job/junior-emulation-engineer-celero-communications-inc/https://jobseveryhour.com/job/junior-emulation-engineer-celero-communications-inc/Tue, 27 Oct 2026 00:00:00 +0000Cordoba, Argentina. , you will help compile, run, and debug RTL on emulation systems, supporting early validation of hardware and firmware ahead of tape-out. You will work closely with RTL design, verification, and firmware teams, learn from senior engineers, and grow into an independent contributor on next-generation semiconductor products. Key Responsibilities Emulation Bring-Up: Support compilation, partitioning, and bring-up of RTL…https://jobseveryhour.com/job/synthesis-sta-engineer-high-speed-serdes-astera-labs/https://jobseveryhour.com/job/synthesis-sta-engineer-high-speed-serdes-astera-labs/Tue, 27 Oct 2026 00:00:00 +0000San Jose, California, United States. Perform RTL synthesis, driving area, power, and timing optimization for digital controller and DSP blocks within high-speed SerDes PHY designs. Author, develop, and validate SDC constraints from scratch, including clock definitions, generated clocks, multi-frequency/multi-mode constraints, I/O delays, false paths, multicycle paths, and clock-domain crossing exceptions unique to SerDes architectures. Set up and…https://jobseveryhour.com/job/photonics-layout-engineer-psiquantum/https://jobseveryhour.com/job/photonics-layout-engineer-psiquantum/Mon, 26 Oct 2026 00:00:00 +0000Palo Alto, California. Quantum computing promises to solve many important problems that could never be solved on any conventional computer. At PsiQuantum, we’re building a general-purpose silicon photonic quantum computer to tackle these very problems. We are looking for an energetic, highly motivated Photonic Layout Engineer who will be responsible for the design, layout, and verification of photonic integrated circuits (PIC) for foundry…https://jobseveryhour.com/job/physical-design-team-lead-astera-labs/https://jobseveryhour.com/job/physical-design-team-lead-astera-labs/Sun, 25 Oct 2026 00:00:00 +0000Tel Aviv-Yafo, Tel Aviv District, Israel. Astera Labs is a hyper-growth connectivity company building the purpose-built silicon that powers rack-scale AI infrastructure. As a Principal Physical Design Engineer and Team Lead in Israel, you will lead physical design teams that take complex, high-speed mixed-signal and digital SoCs from RTL handoff through tapeout. You will set the technical direction, drive execution across multiple projects, and grow the…https://jobseveryhour.com/job/physical-design-engineering-director-astera-labs/https://jobseveryhour.com/job/physical-design-engineering-director-astera-labs/Fri, 23 Oct 2026 00:00:00 +0000Toronto, Ontario, Canada. Astera Labs is seeking a Physical Design Engineering Director to lead a team of physical design engineers at our Toronto site, driving the implementation of connectivity ASICs within our Signal Connectivity Group. This group is responsible for products that enable high-speed serial connectivity including PCIe retimers, Ethernet retimers, and signal conditioning solutions deployed across the world's largest AI…https://jobseveryhour.com/job/talent-acquisition-partner-gtm-f-m-d-moss/https://jobseveryhour.com/job/talent-acquisition-partner-gtm-f-m-d-moss/Fri, 23 Oct 2026 00:00:00 +0000Berlin. Sourcing, screening & managing candidates - identify, attract and engage with talent by using different sourcing techniques and channels. Manage the entire candidate journey from initial contact, coordinating interviews to offer management, ensuring a high quality candidate experience. - Business Partnering - Own full-cycle hiring for your vertical end to end, from sourcing through offer, across Germany, the UK and…https://jobseveryhour.com/job/senior-talent-acquisition-partner-tech-f-m-d-moss/https://jobseveryhour.com/job/senior-talent-acquisition-partner-tech-f-m-d-moss/Fri, 23 Oct 2026 00:00:00 +0000Berlin. Sourcing, screening & managing candidates - identify, attract and engage with talent by using different sourcing techniques and channels. Manage the entire candidate journey from initial contact, coordinating interviews to offer management, ensuring a high quality candidate experience. - Business Partnering - Own full-cycle hiring for your vertical end to end, from sourcing through offer, across all locations. Work…https://jobseveryhour.com/job/senior-electrical-engineer-anduril-industries-3/https://jobseveryhour.com/job/senior-electrical-engineer-anduril-industries-3/Thu, 22 Oct 2026 00:00:00 +0000Costa Mesa, California, United States. We are looking for a Senior Electrical Engineer to join our rapidly growing Air Dominance and Strike team in Costa Mesa, CA . In this role, your primary focus will be full-lifecycle PCB design from concept and schematic capture through board bring-up, test, and debug. In this role you'll also be supporting subsystem cable harnessing, hardware integration, and flight-test operations. If you are a hands-on electrical…https://jobseveryhour.com/job/principal-physical-design-engineer-astera-labs-2/https://jobseveryhour.com/job/principal-physical-design-engineer-astera-labs-2/Thu, 22 Oct 2026 00:00:00 +0000Bengaluru, Karnataka, India. Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software…https://jobseveryhour.com/job/electrical-engineer-intern-skydio/https://jobseveryhour.com/job/electrical-engineer-intern-skydio/Tue, 20 Oct 2026 00:00:00 +0000San Mateo, California, United States. We are seeking interns for our EE Team! We are looking for Electrical Engineering Interns who will help prototype, validate, develop, and refine the electrical systems that bring together state-of-the-art computing hardware, sensing, and power systems in the latest autonomous flying sensors. As a member of the Electrical Engineering team, you will be helping solve tough challenges alongside a team of world-class…https://jobseveryhour.com/job/principal-senior-principal-electrical-design-engineer-astera-labs/https://jobseveryhour.com/job/principal-senior-principal-electrical-design-engineer-astera-labs/Mon, 19 Oct 2026 00:00:00 +0000San Jose, California, United States. We are seeking a Principal Electrical Design Engineer to define and drive the architecture, design, and technical strategy for advanced board-level hardware across next-generation networking and high-performance connectivity platforms. This role encompasses complex hardware systems including chassis boards, NIC cards, PCIe Gen6 platforms, and 800G Ethernet products. This is a principal-level technical leadership…https://jobseveryhour.com/job/partner-solution-consultant-omnissa/https://jobseveryhour.com/job/partner-solution-consultant-omnissa/Fri, 16 Oct 2026 00:00:00 +0000Remote - Germany. Partner Solution Consultant, Omnissa – DACH Region Location: Germany (Remote) Omnissa is empowering the digital workspace. We see in the age of mobile and cloud that consumer devices and application experiences are shaping how businesses drive digital transformation. Consumer experience has changed employee expectations which is creating new application demands and forging new opportunities to change business…https://jobseveryhour.com/job/electromechanical-integration-engineer-air-vehicles-anduril-industries/https://jobseveryhour.com/job/electromechanical-integration-engineer-air-vehicles-anduril-industries/Thu, 15 Oct 2026 00:00:00 +0000Costa Mesa, California, United States. Design flight-critical enclosures, chassis, and mechanical packaging for high-density circuit card assemblies, battery systems, electro-optical payloads, and cable/harness assemblies. Collaborate with electrical engineers to inform PCBA layout, define connector configurations, manage keep-out zones, route harnesses, and establish thermal and grounding interfaces. Create detailed 3D models, drawing packages, and GD&T…https://jobseveryhour.com/job/staff-hardware-engineer-anduril-industries/https://jobseveryhour.com/job/staff-hardware-engineer-anduril-industries/Wed, 14 Oct 2026 00:00:00 +0000Dublin, Dublin, Ireland. The "Schematic Architect" We are seeking an experienced "schematic architect" to fill a critical gap on our Dublin-based hardware team. To be clear, this is not a generalist hardware position. We are looking for a design leader whose primary passion and expertise lie in the early, conceptual stages of electronic design. Think of this role as the architect who creates the blueprint (the schematic), rather than the…https://jobseveryhour.com/job/teach-lead-physical-design-engineer-astera-labs/https://jobseveryhour.com/job/teach-lead-physical-design-engineer-astera-labs/Tue, 13 Oct 2026 00:00:00 +0000Singapore, Singapore. We are seeking a Senior Physical Design Engineer to join our high-performance design team working on next-generation transceiver IPs targeting the TSMC 3nm and advanced technology nodes Key Responsibilities Perform block-level and top-level physical implementation including floorplanning, placement, clock tree synthesis (CTS), routing, and physical verification for high-speed designs in advanced technology nodes…https://jobseveryhour.com/job/principal-physical-design-engineer-astera-labs/https://jobseveryhour.com/job/principal-physical-design-engineer-astera-labs/Tue, 13 Oct 2026 00:00:00 +0000Singapore, Singapore. We are seeking a Senior Physical Design Engineer to join our high-performance design team working on next-generation transceiver IPs targeting the TSMC 3nm and advanced technology nodes Key Responsibilities Perform block-level and top-level physical implementation including floorplanning, placement, clock tree synthesis (CTS), routing, and physical verification for high-speed designs in advanced technology nodes…https://jobseveryhour.com/job/tech-lead-analog-mixed-signal-ic-layout-engineer-astera-labs/https://jobseveryhour.com/job/tech-lead-analog-mixed-signal-ic-layout-engineer-astera-labs/Tue, 13 Oct 2026 00:00:00 +0000Singapore, Singapore. Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software…https://jobseveryhour.com/job/senior-analog-mixed-signal-ic-layout-engineer-astera-labs/https://jobseveryhour.com/job/senior-analog-mixed-signal-ic-layout-engineer-astera-labs/Tue, 13 Oct 2026 00:00:00 +0000Singapore, Singapore. Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software…https://jobseveryhour.com/job/senior-analog-ic-design-engineer-arago/https://jobseveryhour.com/job/senior-analog-ic-design-engineer-arago/Tue, 13 Oct 2026 00:00:00 +0000Paris Offices. Design high-performance analog and mixed-signal ICs optimized for precision, power, and area, driving Arago’s prototype and product iterations from architecture to silicon validation. RESPONSIBILITIES - Design and simulate analog and RF integrated circuits, including critical blocks such as amplifiers, mixers, PLLs, ADCs, DACs, and bias/reference circuits, with a focus on signal integrity, linearity, and precision…https://jobseveryhour.com/job/principal-mixed-analog-design-engineer-astera-labs/https://jobseveryhour.com/job/principal-mixed-analog-design-engineer-astera-labs/Mon, 12 Oct 2026 00:00:00 +0000Irvine, California, United States. Astera Labs is redefining the connectivity that powers rack-scale AI infrastructure, and analog design is at the heart of it. As a Principal Analog Design Engineer, you will architect and design the high-performance analog and mixed-signal circuits that anchor our SerDes, PHY, and high-speed I/O — the silicon building blocks that move data at the speed AI demands. Your work directly shapes the performance, power…https://jobseveryhour.com/job/principal-physical-design-engineer-astera-labs-4/https://jobseveryhour.com/job/principal-physical-design-engineer-astera-labs-4/Mon, 12 Oct 2026 00:00:00 +0000Ahmedabad, Gujarat, India. Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software…https://jobseveryhour.com/job/principal-physical-design-cad-engineer-astera-labs-2/https://jobseveryhour.com/job/principal-physical-design-cad-engineer-astera-labs-2/Sun, 11 Oct 2026 00:00:00 +0000Haifa District, Israel. Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, We are looking for a Physical Design CAD Engineer with at least 3 years of hands-on experience in digital implementation flows. The ideal candidate is highly technical, curious, and…https://jobseveryhour.com/job/staff-photonics-design-pdk-modeling-engineer-lightmatter/https://jobseveryhour.com/job/staff-photonics-design-pdk-modeling-engineer-lightmatter/Thu, 08 Oct 2026 00:00:00 +0000Boston, MA; Mountain View, CA; Toronto, ON. , you will develop our internal Process Design Kit (PDK). You will act as the architect of our component library, bridging the gap between photonics device design and system-level verification. You will develop robust compact models for active and passive components, ensuring that our simulation environment accurately predicts the behavior of our physical layouts. You will work heavily in Python, EDA tools, applying…https://jobseveryhour.com/job/physical-design-engineer-sk-hynix-memory-solutions-america-inc/https://jobseveryhour.com/job/physical-design-engineer-sk-hynix-memory-solutions-america-inc/Wed, 07 Oct 2026 00:00:00 +0000San Jose. Join our Physical Design (SoC Integration) team responsible for delivering high-performance SoC designs from RTL to GDS. As a Sr. Staff Physical Design Engineer, you will lead physical implementation efforts for advanced-node designs, driving critical blocks through synthesis, placement, CTS, routing, and signoff. You will work closely with front-end, DFT, power, and analog teams to optimize PPA (Power, Performance…https://jobseveryhour.com/job/digital-asic-design-engineer-attotude/https://jobseveryhour.com/job/digital-asic-design-engineer-attotude/Wed, 07 Oct 2026 00:00:00 +0000Nuremberg, Germany. We are seeking an experienced Digital IC Design Engineer to join our growing team. In this role, you will be part of an experienced design team developing cutting-edge DSP and mixed-signal ICs. This is a hands-on technical position that requires in-depth technical expertise, and the ability to work in a team of highly experienced engineers to accomplish the goals. Key Responsibilities Flow system level requirements…https://jobseveryhour.com/job/business-recruiter-apac-openai/https://jobseveryhour.com/job/business-recruiter-apac-openai/Tue, 06 Oct 2026 00:00:00 +0000Singapore. Own end-to-end hiring for APAC roles, from scoping and calibration through to offer and close. - Partner closely with senior business leaders to deeply understand team needs, define hiring strategies, and translate business priorities into actionable talent plans. - Build and execute proactive, data-informed sourcing strategies to attract high-calibre and diverse talent across competitive markets. - Act as a trusted…https://jobseveryhour.com/job/senior-firmware-sw-engineer-astera-labs/https://jobseveryhour.com/job/senior-firmware-sw-engineer-astera-labs/Sun, 04 Oct 2026 00:00:00 +0000Tel Aviv-Yafo, Tel Aviv District, Israel. and Its Impact Our firmware team develops the embedded firmware that brings Astera Labs' compute connectivity silicon to life, from boot and initialization through link management, telemetry, error handling, and diagnostics. This firmware runs on the embedded processors inside our chips and ships in data centers powering AI infrastructure around the world. Beyond the firmware, the team also develops the COSMOS SDK…https://jobseveryhour.com/job/customer-success-engineer-japan-rescale/https://jobseveryhour.com/job/customer-success-engineer-japan-rescale/Thu, 01 Oct 2026 00:00:00 +0000Tokyo. Lead and execute all technical activities throughout the customer’s post-sales engagement, such as product and feature adoption, technical presentations, and customer business review meetings. Our top-performing CSEs increase our strategic customers’ usage by over 140% annually. - Independently analyze technical needs, requirements, the customer’s current infrastructure, operations, and workflows. Typically, our…https://jobseveryhour.com/job/senior-pcb-design-engineer-intelligence-systems-anduril-industries/https://jobseveryhour.com/job/senior-pcb-design-engineer-intelligence-systems-anduril-industries/Wed, 30 Sep 2026 00:00:00 +0000Reston, Virginia, United States. We are looking for a Senior PCB Layout Designer to join our rapidly growing team in Reston, Virginia. In this role, you will be responsible for Full Cycle PCB design including collecting requirements, schematic design, component selection, supervision or completion of layout, bring-up, test, debug and integration with the system. WHAT YOU’LL DO Work directly with engineers to produce printed circuit board designs…https://jobseveryhour.com/job/hardware-board-validation-engineering-director-astera-labs/https://jobseveryhour.com/job/hardware-board-validation-engineering-director-astera-labs/Wed, 30 Sep 2026 00:00:00 +0000San Jose, California, United States. Astera Labs is seeking a Director of Hardware Board Validation Engineering to lead the development, bring-up, and validation of board products that enable rack-scale AI infrastructure. Working closely with ASIC, systems, firmware, signal integrity, power integrity, mechanical, thermal, manufacturing, and customer engineering teams, you will guide products from concept and architecture through qualification and mass…https://jobseveryhour.com/job/pcb-layout-designer-re-build-manufacturing/https://jobseveryhour.com/job/pcb-layout-designer-re-build-manufacturing/Wed, 30 Sep 2026 00:00:00 +0000Rochester, NY. if you enjoy solving complex layout challenges, creating consistent design standards, and collaborating across engineering disciplines. This full-time role is based in the Rochester, NY area with flexible remote work options and periodic on-site collaboration. What You Get To Do Design complex multi-layer PCBs (6+ layers) from schematic collection through manufacturing release, including high-speed, controlled…https://jobseveryhour.com/job/senior-pcb-designer-re-build-manufacturing/https://jobseveryhour.com/job/senior-pcb-designer-re-build-manufacturing/Wed, 30 Sep 2026 00:00:00 +0000Rochester, NY. About Re:Build At Re:Build, our mission is to ensure the next generation of important products are made, at scale, in America. We are laying the foundation for a better future for our customers, employees, and communities by revitalizing America's manufacturing base and creating meaningful jobs across the country, including in historically deindustrialized regions. We operate an advanced, end-to-end manufacturing…https://jobseveryhour.com/job/tech-lead-digital-design-engineer-astera-labs/https://jobseveryhour.com/job/tech-lead-digital-design-engineer-astera-labs/Wed, 30 Sep 2026 00:00:00 +0000San Jose, California, United States. Astera Labs is seeking a Tech Lead Engineer to drive front-end digital design for high-performance switch ASICs that enable rack-scale AI infrastructure. In CCE2, you will translate microarchitecture into robust RTL and lead block-level execution across synthesis, timing, verification, DFT, and physical implementation. This is an opportunity to own critical connectivity technology from architecture through GDS while…https://jobseveryhour.com/job/electrical-engineer-alten-technology-usa/https://jobseveryhour.com/job/electrical-engineer-alten-technology-usa/Tue, 29 Sep 2026 00:00:00 +0000Twinsburg, Ohio, United States. Provide engineering support to manufacturing operations and contribute to ongoing product enhancements. Analyze, diagnose, and troubleshoot both analog and digital electronic circuits. Develop, review, and carry out engineering test procedures, records, and supporting documentation. Contribute to design reviews with internal engineering teams as well as external suppliers. Assist with verification and validation…https://jobseveryhour.com/job/product-lead-encord/https://jobseveryhour.com/job/product-lead-encord/Tue, 29 Sep 2026 00:00:00 +0000London. Encord is a fast-growing company building the data infrastructure layer for AI teams. We work with leading enterprises across autonomous vehicles, healthcare, robotics, and generative AI. Our product team is small, high-calibre, and operating in green-field territory. The data layer for AI is still being defined, and you will help define it. As Product Lead, you will own a meaningful slice of the product, spanning…https://jobseveryhour.com/job/design-verification-emulation-hardware-river-ai-inc/https://jobseveryhour.com/job/design-verification-emulation-hardware-river-ai-inc/Mon, 28 Sep 2026 00:00:00 +0000Austin, TX, Palo Alto, CA. We are seeking an emulation-focused design verification engineer to drive IP and SoC verification on emulation platforms. Working with simulation-based DV teams, you will translate architectural and microarchitectural definitions into workloads suited to emulation, then adapt and run those tests. You will partner with DV block owners on debug and emulation-specific closure, providing emulation signoff as an input to…https://jobseveryhour.com/job/mixed-signal-ic-layout-engineer-tenstorrent/https://jobseveryhour.com/job/mixed-signal-ic-layout-engineer-tenstorrent/Mon, 28 Sep 2026 00:00:00 +0000Santa Clara, California, United States. focuses on high quality, high-speed analog/mixed-signal blocks and their integration into larger SoCs. This role is remote, based out of any in the United States. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who you are An…https://jobseveryhour.com/job/dft-architect-physical-design-chiplet-envision-employment-solutions/https://jobseveryhour.com/job/dft-architect-physical-design-chiplet-envision-employment-solutions/Sun, 27 Sep 2026 00:00:00 +0000New Cairo City, Cairo Governorate, Egypt. Testing a single die is hard enough. Testing a system of chiplets means rethinking test access, coverage and diagnosis from the ground up. You'll define the DFT architecture for complex, multi die designs and make sure it works hand in hand with physical design. WHAT YOU'LL DO Define DFT architecture and strategy for SoC and chiplet based designs Own test access across dies, including JTAG, IJTAG and IEEE 1500/1838…https://jobseveryhour.com/job/senior-eda-cad-engineer-envision-employment-solutions/https://jobseveryhour.com/job/senior-eda-cad-engineer-envision-employment-solutions/Sun, 27 Sep 2026 00:00:00 +0000New Cairo City, Cairo Governorate, Egypt. Every simulation, regression and signoff run depends on the tools and infrastructure you build. You'll own the EDA flows and CAD environment behind full SoC development, from licensing and compute farms to CI/CD and AI assisted tooling, so the design teams can focus on the chip and not on the tools. WHAT YOU'LL DO Define, deploy and maintain EDA flows for simulation, synthesis, place and route, DFT and signoff…https://jobseveryhour.com/job/senior-rtl-design-engineer-envision-employment-solutions/https://jobseveryhour.com/job/senior-rtl-design-engineer-envision-employment-solutions/Sun, 27 Sep 2026 00:00:00 +0000New Cairo City, Cairo Governorate, Egypt. You'll take a design from architecture to tapeout, defining the microarchitecture, writing the RTL, and making sure it's clean enough for synthesis, timing and test teams to build on. It's hands on design work on complex SoCs, with a real say in how each unit is built. WHAT YOU'LL DO Own feasibility studies and help define system architecture, requirements and external interfaces Develop microarchitecture and logic…https://jobseveryhour.com/job/sr-staff-principal-physical-design-engineer-sk-hynix-memory-solutions-america-inc/https://jobseveryhour.com/job/sr-staff-principal-physical-design-engineer-sk-hynix-memory-solutions-america-inc/Fri, 25 Sep 2026 00:00:00 +0000San Jose. Join our Physical Design (SoC Integration) team responsible for delivering high-performance SoC designs from RTL to GDS. As a Sr. Staff Physical Design Engineer, you will lead physical implementation efforts for advanced-node designs, driving critical blocks through synthesis, placement, CTS, routing, and signoff. You will work closely with front-end, DFT, power, and analog teams to optimize PPA (Power, Performance…https://jobseveryhour.com/job/lead-sta-engineer-envision-employment-solutions/https://jobseveryhour.com/job/lead-sta-engineer-envision-employment-solutions/Sat, 26 Sep 2026 00:00:00 +0000New Cairo City, Cairo Governorate, Egypt. Timing signoff is the final word on whether a chip is ready, and you'll be the one giving it. As the lead STA specialist, you'll set the timing methodology, guide the team through closure, and make the call on what's truly clean. You'll be the reference point for anyone who needs to understand why a path is failing and what it will take to fix it. WHAT YOU'LL DO Lead full chip and block level STA and timing signoff…https://jobseveryhour.com/job/senior-dft-engineer-envision-employment-solutions/https://jobseveryhour.com/job/senior-dft-engineer-envision-employment-solutions/Sat, 26 Sep 2026 00:00:00 +0000New Cairo City, Cairo Governorate, Egypt. A chip that can't be tested can't ship. You'll own design for test on large, complex SoCs, making sure every block can be scanned, patterned and diagnosed, and that test coverage stays high without costing the design its timing or area budget. WHAT YOU'LL DO Implement DFT in line with established test methodology on advanced process nodes Perform top and block level DFT insertion: scan compression, JTAG and IJTAG…https://jobseveryhour.com/job/senior-physical-design-engineer-floorplan-pnr-envision-employment-solutions/https://jobseveryhour.com/job/senior-physical-design-engineer-floorplan-pnr-envision-employment-solutions/Sat, 26 Sep 2026 00:00:00 +0000New Cairo City, Cairo Governorate, Egypt. A good floorplan makes every stage that follows easier, and a bad one haunts the project to tapeout. You'll own the implementation side of physical design, from partitioning and power planning through placement, CTS and routing, on some of the most advanced technology nodes out there. WHAT YOU'LL DO Own floorplanning, partitioning, pin assignment and power mesh design at block and full chip level Run placement, CTS…https://jobseveryhour.com/job/senior-physical-design-engineer-synthesis-sdc-sta-envision-employment-solutions/https://jobseveryhour.com/job/senior-physical-design-engineer-synthesis-sdc-sta-envision-employment-solutions/Sat, 26 Sep 2026 00:00:00 +0000New Cairo City, Cairo Governorate, Egypt. Every constraint you write decides whether a chip closes timing or slips a tapeout. You'll own the front end of the physical design flow on advanced nodes, turning RTL into clean netlists with constraints that hold from synthesis all the way to signoff. When the timing report looks wrong, you're the one who knows whether it's the design, the constraint, or the tool. WHAT YOU'LL DO Own synthesis for complex blocks…https://jobseveryhour.com/job/principal-analog-mixed-signal-design-engineer-astera-labs/https://jobseveryhour.com/job/principal-analog-mixed-signal-design-engineer-astera-labs/Fri, 25 Sep 2026 00:00:00 +0000Toronto, Ontario, Canada. Astera Labs is redefining the connectivity that powers rack-scale AI infrastructure, and analog design is at the heart of it. As a Principal Analog Mixed Signal Design Engineer, you will architect and design the high-performance analog and mixed-signal circuits that anchor our SerDes, PHY, and high-speed I/O — the silicon building blocks that move data at the speed AI demands. Your work directly shapes the…https://jobseveryhour.com/job/staff-pcb-layout-engineer-graphcore/https://jobseveryhour.com/job/staff-pcb-layout-engineer-graphcore/Thu, 24 Sep 2026 00:00:00 +0000Austin, Texas, United States. Create, verify, and maintain schematic symbols, PCB footprints, and associated 3D models. Validate component pin assignments, dimensions, land patterns, and library attributes against manufacturer documentation. Maintain library naming conventions, revision control, and component approval processes. Develop PCB layouts from approved schematics, including component placement, routing, stackup coordination, and design…https://jobseveryhour.com/job/quantum-design-enablement-engineer-ionq/https://jobseveryhour.com/job/quantum-design-enablement-engineer-ionq/Wed, 23 Sep 2026 00:00:00 +0000College Park, Maryland, United States. , you will serve as the primary technical interface between internal quantum chip designers and external foundry partners, playing a key role in bringing next-generation trapped-ion hardware to life. You will ensure our quantum chip designs transition seamlessly into reliable, scalable fabrication. Core responsibilities include managing the tapeout flow, executing physical verification, performing hands-on layout…https://jobseveryhour.com/job/principal-high-speed-analog-layout-design-engineer-celero-communications-inc-3/https://jobseveryhour.com/job/principal-high-speed-analog-layout-design-engineer-celero-communications-inc-3/Mon, 21 Sep 2026 00:00:00 +0000Ottawa, Ontario, Canada. Lead and own the physical layout design of complex analog/mixed-signal macros (e.g., ADCs, DACs, PLLs), from floor planning through final verification • Collaborate closely with schematic designers to create optimal layout solutions considering performance, matching, symmetry, and reliability • Mentor and guide junior layout engineers/contractors across multiple time zones, enforcing best practices in layout design…https://jobseveryhour.com/job/principal-high-speed-analog-layout-design-engineer-celero-communications-inc-2/https://jobseveryhour.com/job/principal-high-speed-analog-layout-design-engineer-celero-communications-inc-2/Mon, 21 Sep 2026 00:00:00 +0000San Jose, CA. Lead and own the physical layout design of complex analog/mixed-signal macros (e.g., ADCs, DACs, PLLs), from floor planning through final verification • Collaborate closely with schematic designers to create optimal layout solutions considering performance, matching, symmetry, and reliability • Mentor and guide junior layout engineers/contractors across multiple time zones, enforcing best practices in layout design…https://jobseveryhour.com/job/principal-high-speed-analog-layout-design-engineer-celero-communications-inc/https://jobseveryhour.com/job/principal-high-speed-analog-layout-design-engineer-celero-communications-inc/Mon, 21 Sep 2026 00:00:00 +0000Irvine, CA. Lead and own the physical layout design of complex analog/mixed-signal macros (e.g., ADCs, DACs, PLLs), from floor planning through final verification • Collaborate closely with schematic designers to create optimal layout solutions considering performance, matching, symmetry, and reliability • Mentor and guide junior layout engineers/contractors across multiple time zones, enforcing best practices in layout design…https://jobseveryhour.com/job/high-speed-analog-layout-design-engineer-celero-communications-inc/https://jobseveryhour.com/job/high-speed-analog-layout-design-engineer-celero-communications-inc/Mon, 21 Sep 2026 00:00:00 +0000Córdoba, Argentina. Lead and own the physical layout design of complex analog/mixed-signal macros (e.g., ADCs, DACs, PLLs), from floor planning through final verification • Collaborate closely with schematic designers to create optimal layout solutions considering performance, matching, symmetry, and reliability • Mentor and guide junior layout engineers/contractors across multiple time zones, enforcing best practices in layout design…https://jobseveryhour.com/job/principal-physical-verification-engineer-celero-communications-inc-2/https://jobseveryhour.com/job/principal-physical-verification-engineer-celero-communications-inc-2/Mon, 21 Sep 2026 00:00:00 +0000San Jose, CA. Team & Project Leadership • Lead full chip Physical Verification effort • Own execution plans, schedules for full-chip • Drive accountability for quality, milestones, and tapeout readiness. • Conduct full chip and blocks PV checks Physical Verification Ownership • Ownership of full chip verification • Work with internal analog team to ensure clean IP delivery • Responsible for running and analyzing DRC/ERC/LUP/PERC…https://jobseveryhour.com/job/principal-physical-verification-engineer-celero-communications-inc/https://jobseveryhour.com/job/principal-physical-verification-engineer-celero-communications-inc/Mon, 21 Sep 2026 00:00:00 +0000Irvine, CA. Team & Project Leadership • Lead full chip Physical Verification effort • Own execution plans, schedules for full-chip • Drive accountability for quality, milestones, and tapeout readiness. • Conduct full chip and blocks PV checks Physical Verification Ownership • Ownership of full chip verification • Work with internal analog team to ensure clean IP delivery • Responsible for running and analyzing DRC/ERC/LUP/PERC…https://jobseveryhour.com/job/principal-analog-mixed-signal-design-engineer-astera-labs-2/https://jobseveryhour.com/job/principal-analog-mixed-signal-design-engineer-astera-labs-2/Fri, 18 Sep 2026 00:00:00 +0000Ho Chi Minh City, Vietnam. We are seeking an experienced Analog/Mixed-Signal (AMS) Circuit Design Engineer to join our high-performance design team working on next-generation transceiver IPs targeting the FinFET technology node. In this role, you will design high-speed analog and mixed-signal circuits used in multi-gigabit transceivers, collaborating with layout, verification, and system teams to ensure robust performance, power efficiency…https://jobseveryhour.com/job/principal-dft-engineer-celero-communications-inc/https://jobseveryhour.com/job/principal-dft-engineer-celero-communications-inc/Wed, 16 Sep 2026 00:00:00 +0000Irvine, California, United States. Develop and implement DFT architecture for ASIC and SoC designs. Perform scan insertion, scan chain planning, and scan compression implementation. Generate and validate ATPG patterns and analyze fault coverage results. Implement and verify MBIST, and other on-chip test features. Collaborate with RTL, verification, and physical design teams to ensure successful DFT integration. Support JTAG and boundary-scan…https://jobseveryhour.com/job/tech-lead-sta-astera-labs/https://jobseveryhour.com/job/tech-lead-sta-astera-labs/Tue, 15 Sep 2026 00:00:00 +0000Hyderabad, Telangana, India. Astera Labs is hiring a Principal Engineer, Static Timing Analysis to own top-level timing closure and signoff for our next-generation connectivity silicon powering rack-scale AI infrastructure. In this role, you'll drive full-chip STA strategy across advanced process nodes, partner with physical design, RTL, DFT, and CAD teams, and ensure first-pass timing success on some of the most complex SoCs in the industry…https://jobseveryhour.com/job/senior-rf-engineer-cowboyspace/https://jobseveryhour.com/job/senior-rf-engineer-cowboyspace/Tue, 15 Sep 2026 00:00:00 +0000San Carlos, California. The Avionics Team is looking for an RF Engineer to design, develop, and validate the RF hardware that enables communication, telemetry, command and control, and high-bandwidth data transport across our spacecraft platforms. This role is heavily focused on board-level RF design and integration, working closely with electrical, PCB layout, firmware, and test engineers to deliver high-performance RF subsystems capable…https://jobseveryhour.com/job/principal-sr-principal-digital-design-engineer-astera-labs/https://jobseveryhour.com/job/principal-sr-principal-digital-design-engineer-astera-labs/Mon, 14 Sep 2026 00:00:00 +0000Taipei, Taiwan. Join Astera Labs as a Principal Digital Design Engineer to architect and implement next-generation digital designs for high-performance AI connectivity solutions. You'll own complex blocks from micro-architecture through silicon bring-up, driving RTL implementation and collaborating with verification, physical design, and DFT teams to deliver production-quality silicon supporting PCIe Gen 6/7, CXL, UALink, UCI…https://jobseveryhour.com/job/electrical-engineer-manufacturing-anduril-industries/https://jobseveryhour.com/job/electrical-engineer-manufacturing-anduril-industries/Mon, 14 Sep 2026 00:00:00 +0000Atlanta, Georgia, United States. PCBA Design for Manufacturability & Assembly (DFM / DFA): Partner directly with Electrical Hardware Design Engineers during schematic capture and layout to optimize complex multilayer rigid and rigid-flex boards for automated SMT production. Review board layouts in Altium Designer, Cadence Allegro, or Mentor Graphics to verify pad geometries, solder mask dams, trace clearances, via-in-pad plating, and component…https://jobseveryhour.com/job/principal-analog-mixed-signal-design-engineer-astera-labs-3/https://jobseveryhour.com/job/principal-analog-mixed-signal-design-engineer-astera-labs-3/Fri, 11 Sep 2026 00:00:00 +0000San Jose, California, United States. Astera Labs is redefining the connectivity that powers rack-scale AI infrastructure, and analog design is at the heart of it. As a Principal Analog Design Engineer, you will architect and design the high-performance analog and mixed-signal circuits that anchor our SerDes, PHY, and high-speed I/O — the silicon building blocks that move data at the speed AI demands. Your work directly shapes the performance, power…https://jobseveryhour.com/job/senior-sta-engineer-astera-labs/https://jobseveryhour.com/job/senior-sta-engineer-astera-labs/Fri, 11 Sep 2026 00:00:00 +0000Ahmedabad, Gujarat, India. Position: Senior STA Engineer Experience: 6+ years Location: Ahmedabad Employment Type: Full-time Job Summary We are looking for a Senior STA Engineer with strong expertise in Static Timing Analysis, timing signoff, and timing closure for complex ASIC/SoC designs. The candidate will own timing analysis activities across the design flow and work closely with RTL, Synthesis, Physical Design, and Signoff teams to…https://jobseveryhour.com/job/senior-digital-design-engineer-astera-labs/https://jobseveryhour.com/job/senior-digital-design-engineer-astera-labs/Thu, 10 Sep 2026 00:00:00 +0000Toronto, Ontario, Canada. As a Senior Digital Design Engineer, you will design and integrate high-performance connectivity silicon for the next generation of AI infrastructure. You will contribute across architecture, micro-architecture, RTL implementation, synthesis, timing closure, and IP integration for PCIe and Ethernet controllers, bridges, switches, and related SerDes interfaces. You will work with cross-functional teams to turn…https://jobseveryhour.com/job/principal-electrical-design-engineer-astera-labs/https://jobseveryhour.com/job/principal-electrical-design-engineer-astera-labs/Thu, 03 Sep 2026 00:00:00 +0000San Jose, California, United States. Principal Electrical Design Engineer Board Hardware Engineering About the Role We are seeking a Principal Electrical Design Engineer to define and drive the architecture, design, and technical strategy for advanced board-level hardware across next-generation networking and high-performance connectivity platforms. This role encompasses complex hardware systems including chassis boards, NIC cards, PCIe Gen6 platforms…https://jobseveryhour.com/job/pcb-layout-engineer-robotics-openai/https://jobseveryhour.com/job/pcb-layout-engineer-robotics-openai/Tue, 01 Sep 2026 00:00:00 +0000San Francisco. We are looking for a PCB Layout Engineer to design high-density electronics for next-generation robotic systems. You will own PCB layout from floor planning through fabrication release, working closely with electrical, SI/PI, mechanical, and manufacturing teams. This role is based in San Francisco and requires in-person presence four days per week. In this role, you will: - Own PCB layout, component placement…https://jobseveryhour.com/job/principal-electrical-engineer-smart-cable-modules-astera-labs/https://jobseveryhour.com/job/principal-electrical-engineer-smart-cable-modules-astera-labs/Thu, 27 Aug 2026 00:00:00 +0000San Jose, California, United States. Principal Electrical Engineer – Smart Cable Modules Active Copper Cable & Pluggable Module Design | Hardware Engineering About the Role We are looking for a Principal Electrical Engineer to take strategic ownership of our Smart Cable Module (SCM) hardware platform. This is a senior individual-contributor role that combines deep technical leadership with cross-organizational influence - you will define the electrical…https://jobseveryhour.com/job/hardware-engineer-test-openai/https://jobseveryhour.com/job/hardware-engineer-test-openai/Thu, 27 Aug 2026 00:00:00 +0000San Francisco. you will: - As a Hardware Test Engineer, you will work on Machine Learning/AI hardware system projects to craft the solutions for current and future data center deployments. - You will bring a strong understanding of hardware system testing, excellent project management skills, and the ability to collaborate across multiple teams to ensure efficient lab operations. - You will be responsible for designing…https://jobseveryhour.com/job/ecad-librarian-apptronik/https://jobseveryhour.com/job/ecad-librarian-apptronik/Wed, 26 Aug 2026 00:00:00 +0000Austin, TX. We're looking for a detail-oriented ECAD Librarian to own and grow our Altium component library, ensuring every schematic symbol, PCB footprint, and 3D model is accurate, standardized, and manufacturable. In this role, you will partner closely with electrical, mechanical, and manufacturing engineers to keep the library current, enforce design and naming standards, and make sure components meet IPC and DFM best…https://jobseveryhour.com/job/staff-sr-staff-electro-optic-link-codesign-engineer-lightmatter/https://jobseveryhour.com/job/staff-sr-staff-electro-optic-link-codesign-engineer-lightmatter/Tue, 25 Aug 2026 00:00:00 +0000Boston, MA; Mountain View, CA. Develop, own, and continuously improve electro-optic link simulation models covering photonic device, propagation, and channel BER — from electron to photon to electron. Build multi-physics models that combine optical propagation (VPI Photonics, Lumerical INTERCONNECT / FDTD, sax), analog circuit behavior (Cadence Virtuoso / Spectre, Verilog-A)) into a coherent link analysis framework. Execute comprehensive corner…