Synthesis & Static Timing Analysis (STA) Engineer is open at Voltai.careers in Palo Alto Office. The posting gives no salary; similar roles in the United States advertise a median of $190K. Posted on Oct 19, 2026, and still on Voltai.careers’s careers page when we last checked, on Nov 15, 2026.
About the role
Own logic synthesis and constraint development (SDC) for blocks and full chips. - Drive timing closure across corners and modes, working with RTL and physical design teams. - Run and sign off STA, including on-chip variation, crosstalk, and multi-corner multi-mode analysis. - Perform logic equivalence checking between RTL and netlist. - Build automation that makes synthesis and timing flows faster and more reliable…
The opening lines of the posting. The rest is on Voltai.careers’s careers page.
Hiring at Voltai.careers
Voltai.careers has 33 open roles right now, 2 of them remote. Most are in Engineering, Operations and Data & Research. See all its roles
