Principal PLL Design Engineer is open at Celero Communications, Inc. in Irvine, CA or San Jose, CA. The posting gives a salary of $150K - $250K. Posted on Apr 6, 2026, and still on Celero Communications, Inc.’s careers page when we last checked, on Nov 14, 2026.
About the role
, you will architect and design state-of-the-art PLLs for industry-leading transceivers, working alongside a world-class team to solve some of the most challenging mixed-signal design problems in advanced CMOS technologies. This is an opportunity to make a significant technical impact while helping build groundbreaking products from the ground up. Locations : Irvine, CA (HQ) | San Jose, CA | Vancouver, BC | Ottawa…
The opening lines of the posting. The rest is on Celero Communications, Inc.’s careers page.
Hiring at Celero Communications, Inc.
Celero Communications, Inc. has 26 open roles right now. Most are in Engineering, Marketing & Community and Operations. The median advertised salary across its roles with a published range is $200K. See all its roles
