Principal Physical Design Engineer, STA is open at Astera Labs in San Jose, California, United States. The posting gives a salary of $209K - $250K. Posted on May 20, 2026, and still on Astera Labs’s careers page when we last checked, on Nov 14, 2026.
About the role
Drive timing closure from RTL through sign-off, ensuring robust timing across complex SoCs. Develop and validate SDC constraints, including MMMC setup, to enable accurate and efficient STA analysis. Define and manage I/O timing budgets across hierarchical designs. Apply advanced sign-off methodologies at TSMC 7nm and below, including OCV/AOCV and PVT effects. Leverage ETM libraries for hierarchical timing analysis…
The opening lines of the posting. The rest is on Astera Labs’s careers page.
Hiring at Astera Labs
Astera Labs has 173 open roles right now. Most are in Engineering, Design and Supply Chain & Logistics. The median advertised salary across its roles with a published range is $212K. See all its roles
