Principal High-Speed Analog Layout Design Engineer is open at Celero Communications, Inc. in San Jose, CA. The posting gives a salary of $150K - $250K. Posted on Sep 21, 2026, and still on Celero Communications, Inc.’s careers page when we last checked, on Nov 14, 2026.
About the role
Lead and own the physical layout design of complex analog/mixed-signal macros (e.g., ADCs, DACs, PLLs), from floor planning through final verification • Collaborate closely with schematic designers to create optimal layout solutions considering performance, matching, symmetry, and reliability • Mentor and guide junior layout engineers/contractors across multiple time zones, enforcing best practices in layout design…
The opening lines of the posting. The rest is on Celero Communications, Inc.’s careers page.
Hiring at Celero Communications, Inc.
Celero Communications, Inc. has 26 open roles right now. Most are in Engineering, Marketing & Community and Operations. The median advertised salary across its roles with a published range is $200K. See all its roles
