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Design Verification Engineer

Voltai.careers · Palo Alto Office
Open 368 daysPythonLLMVerilog

Design Verification Engineer is open at Voltai.careers in Palo Alto Office. The posting gives no salary; similar roles in the United States advertise a median of $190K. Posted on Nov 12, 2025, and still on Voltai.careers’s careers page when we last checked, on Nov 15, 2026.

About the role

Own verification strategy across multiple IP blocks and subsystems, from testbench - architecture to signoff. - Design and develop AI assisted workflows that accelerate verification, coverage closure, and debug. - Build reusable verification frameworks using SystemVerilog, UVM, Python and custom automation tooling. - Collaborate with ML and software teams to integrate AI models into existing DV environments. -…

The opening lines of the posting. The rest is on Voltai.careers’s careers page.

Hiring at Voltai.careers

Voltai.careers has 33 open roles right now, 2 of them remote. Most are in Engineering, Operations and Data & Research. See all its roles

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